* [PATCH 0/4] iWave G21D-Q7 enable PCIe, flash, CAN and SD2 LED @ 2020-08-25 16:27 Lad Prabhakar 2020-08-25 16:27 ` [PATCH 1/4] ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller Lad Prabhakar ` (3 more replies) 0 siblings, 4 replies; 19+ messages in thread From: Lad Prabhakar @ 2020-08-25 16:27 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, linux-renesas-soc, devicetree Cc: linux-kernel, Lad Prabhakar, Prabhakar Hi All, This patch series enables PCIe, SPI NOR flash, CAN0 and SD2 LED indication on iWave G21D-Q7 board. Patches apply on top of [1] and also dependent on patch [2] [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/ renesas-devel.git/log/?h=renesas-arm-dt-for-v5.10 [2] https://patchwork.kernel.org/patch/11712541/ Cheers, Prabhakar Lad Prabhakar (4): ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller ARM: dts: r8a7742-iwg21d-q7: Add SPI NOR support ARM: dts: r8a7742-iwg21d-q7: Add can0 support to carrier board ARM: dts: r8a7742-iwg21d-q7: Enable SD2 LED indication arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 74 +++++++++++++++++++++++++ 1 file changed, 74 insertions(+) -- 2.17.1 ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 1/4] ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller 2020-08-25 16:27 [PATCH 0/4] iWave G21D-Q7 enable PCIe, flash, CAN and SD2 LED Lad Prabhakar @ 2020-08-25 16:27 ` Lad Prabhakar 2020-09-03 10:18 ` Geert Uytterhoeven 2020-10-09 7:23 ` Pavel Machek 2020-08-25 16:27 ` [PATCH 2/4] ARM: dts: r8a7742-iwg21d-q7: Add SPI NOR support Lad Prabhakar ` (2 subsequent siblings) 3 siblings, 2 replies; 19+ messages in thread From: Lad Prabhakar @ 2020-08-25 16:27 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, linux-renesas-soc, devicetree Cc: linux-kernel, Lad Prabhakar, Prabhakar Enable PCIe Controller and set PCIe bus clock frequency. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> --- arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index 9bf4fbd9c736..73300ab46ea6 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -238,6 +238,18 @@ /* status = "okay"; */ }; +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pciec { + /* SW2[6] determines which connector is activated + * ON = PCIe X4 (connector-J7) + * OFF = mini-PCIe (connector-J26) + */ + status = "okay"; +}; + &pfc { avb_pins: avb { groups = "avb_mdio", "avb_gmii"; -- 2.17.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH 1/4] ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller 2020-08-25 16:27 ` [PATCH 1/4] ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller Lad Prabhakar @ 2020-09-03 10:18 ` Geert Uytterhoeven 2020-09-03 11:18 ` Lad, Prabhakar 2020-10-09 7:23 ` Pavel Machek 1 sibling, 1 reply; 19+ messages in thread From: Geert Uytterhoeven @ 2020-09-03 10:18 UTC (permalink / raw) To: Lad Prabhakar Cc: Magnus Damm, Rob Herring, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, Prabhakar Hi Prabhakar, On Tue, Aug 25, 2020 at 6:28 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Enable PCIe Controller and set PCIe bus clock frequency. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.10. One thing to double-check below. > --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > @@ -238,6 +238,18 @@ > /* status = "okay"; */ > }; > > +&pcie_bus_clk { > + clock-frequency = <100000000>; > +}; > + > +&pciec { > + /* SW2[6] determines which connector is activated > + * ON = PCIe X4 (connector-J7) > + * OFF = mini-PCIe (connector-J26) The table on page 14 says it's the other way around. According to the CBTL02042ABQ datasheet, PCIe_SEL = low selects the first channel (PCIe x4), while PCIe_SEL = high selects the second channel (mini-PCIe). Enabling the switch ties the signal low, so the table must be wrong. > + */ > + status = "okay"; > +}; > + > &pfc { > avb_pins: avb { > groups = "avb_mdio", "avb_gmii"; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/4] ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller 2020-09-03 10:18 ` Geert Uytterhoeven @ 2020-09-03 11:18 ` Lad, Prabhakar 2020-09-03 11:29 ` Geert Uytterhoeven 0 siblings, 1 reply; 19+ messages in thread From: Lad, Prabhakar @ 2020-09-03 11:18 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List Hi Geert, Thank you for the review. On Thu, Sep 3, 2020 at 11:18 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Tue, Aug 25, 2020 at 6:28 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Enable PCIe Controller and set PCIe bus clock frequency. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > i.e. will queue in renesas-devel for v5.10. > > One thing to double-check below. > > > --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > > +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > > @@ -238,6 +238,18 @@ > > /* status = "okay"; */ > > }; > > > > +&pcie_bus_clk { > > + clock-frequency = <100000000>; > > +}; > > + > > +&pciec { > > + /* SW2[6] determines which connector is activated > > + * ON = PCIe X4 (connector-J7) > > + * OFF = mini-PCIe (connector-J26) > > The table on page 14 says it's the other way around. > > According to the CBTL02042ABQ datasheet, PCIe_SEL = low > selects the first channel (PCIe x4), while PCIe_SEL = high selects the > second channel (mini-PCIe). > Enabling the switch ties the signal low, so the table must be wrong. > Referring to [1] page 3: SEL = LOW: A↔B SEL = HIGH: A↔C And as per the schematic iW-PREJD-CS-01-R2.0-REL1.5.pdf channel B is J7 (PCIe X 4) and channel C is J26 (mini PCIe slot). Enabling the switch SW2[6] (ON) ties SEL to LOW -> channel B is J7 (PCIe X 4) Disabling the switch SW2[6] (OFF) ties SEL to HIGH -> channel C is J26 (mini PCIe) Also iW-PREJD-CS-01-R2.0-REL1.5.pdf page 14 (General purpose table DIP Switch) mentions the above. [1] https://www.mouser.co.uk/datasheet/2/302/CBTL02042A_CBTL02042B-1126164.pdf Cheers, Prabhakar > > + */ > > + status = "okay"; > > +}; > > + > > &pfc { > > avb_pins: avb { > > groups = "avb_mdio", "avb_gmii"; > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/4] ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller 2020-09-03 11:18 ` Lad, Prabhakar @ 2020-09-03 11:29 ` Geert Uytterhoeven 0 siblings, 0 replies; 19+ messages in thread From: Geert Uytterhoeven @ 2020-09-03 11:29 UTC (permalink / raw) To: Lad, Prabhakar Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List Hi Prabhakar, On Thu, Sep 3, 2020 at 1:18 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Thu, Sep 3, 2020 at 11:18 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Tue, Aug 25, 2020 at 6:28 PM Lad Prabhakar > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > Enable PCIe Controller and set PCIe bus clock frequency. > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > i.e. will queue in renesas-devel for v5.10. > > > > One thing to double-check below. > > > > > --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > > > +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > > > @@ -238,6 +238,18 @@ > > > /* status = "okay"; */ > > > }; > > > > > > +&pcie_bus_clk { > > > + clock-frequency = <100000000>; > > > +}; > > > + > > > +&pciec { > > > + /* SW2[6] determines which connector is activated > > > + * ON = PCIe X4 (connector-J7) > > > + * OFF = mini-PCIe (connector-J26) > > > > The table on page 14 says it's the other way around. > > > > According to the CBTL02042ABQ datasheet, PCIe_SEL = low > > selects the first channel (PCIe x4), while PCIe_SEL = high selects the > > second channel (mini-PCIe). > > Enabling the switch ties the signal low, so the table must be wrong. > > > Referring to [1] page 3: > > SEL = LOW: A↔B > SEL = HIGH: A↔C > > And as per the schematic iW-PREJD-CS-01-R2.0-REL1.5.pdf channel B is > J7 (PCIe X 4) and channel C is J26 (mini PCIe slot). > > Enabling the switch SW2[6] (ON) ties SEL to LOW -> channel B is J7 (PCIe X 4) > Disabling the switch SW2[6] (OFF) ties SEL to HIGH -> channel C is J26 > (mini PCIe) > > Also iW-PREJD-CS-01-R2.0-REL1.5.pdf page 14 (General purpose table DIP > Switch) mentions the above. Oh right, I looked at the old document, and they fixed it in the newer one. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/4] ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller 2020-08-25 16:27 ` [PATCH 1/4] ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller Lad Prabhakar 2020-09-03 10:18 ` Geert Uytterhoeven @ 2020-10-09 7:23 ` Pavel Machek 2020-10-09 9:01 ` Lad, Prabhakar 1 sibling, 1 reply; 19+ messages in thread From: Pavel Machek @ 2020-10-09 7:23 UTC (permalink / raw) To: Lad Prabhakar Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, linux-renesas-soc, devicetree, linux-kernel, Prabhakar [-- Attachment #1: Type: text/plain, Size: 432 bytes --] Hi! > +&pciec { > + /* SW2[6] determines which connector is activated > + * ON = PCIe X4 (connector-J7) > + * OFF = mini-PCIe (connector-J26) > + */ > + status = "okay"; > +}; Note this is wrong comment style for non-network parts of kernel. Best regards, Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 181 bytes --] ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/4] ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller 2020-10-09 7:23 ` Pavel Machek @ 2020-10-09 9:01 ` Lad, Prabhakar 0 siblings, 0 replies; 19+ messages in thread From: Lad, Prabhakar @ 2020-10-09 9:01 UTC (permalink / raw) To: Pavel Machek Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML Hi Pavel, Thank you for the review. On Fri, Oct 9, 2020 at 8:23 AM Pavel Machek <pavel@denx.de> wrote: > > Hi! > > > +&pciec { > > + /* SW2[6] determines which connector is activated > > + * ON = PCIe X4 (connector-J7) > > + * OFF = mini-PCIe (connector-J26) > > + */ > > + status = "okay"; > > +}; > > Note this is wrong comment style for non-network parts of kernel. > Good point, i'll fix that. Cheers, Prabhakar ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 2/4] ARM: dts: r8a7742-iwg21d-q7: Add SPI NOR support 2020-08-25 16:27 [PATCH 0/4] iWave G21D-Q7 enable PCIe, flash, CAN and SD2 LED Lad Prabhakar 2020-08-25 16:27 ` [PATCH 1/4] ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller Lad Prabhakar @ 2020-08-25 16:27 ` Lad Prabhakar 2020-09-03 11:59 ` Geert Uytterhoeven 2020-08-25 16:27 ` [PATCH 3/4] ARM: dts: r8a7742-iwg21d-q7: Add can0 support to carrier board Lad Prabhakar 2020-08-25 16:27 ` [PATCH 4/4] ARM: dts: r8a7742-iwg21d-q7: Enable SD2 LED indication Lad Prabhakar 3 siblings, 1 reply; 19+ messages in thread From: Lad Prabhakar @ 2020-08-25 16:27 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, linux-renesas-soc, devicetree Cc: linux-kernel, Lad Prabhakar, Prabhakar Add support for the SPI NOR device which is connected to MSIOF0 interface on the iWave RainboW-G21d-q7 board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> --- arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 31 +++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index 73300ab46ea6..e709a132f2f7 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -220,6 +220,32 @@ status = "okay"; }; +&msiof0 { + pinctrl-0 = <&msiof0_pins>; + pinctrl-names = "default"; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + + status = "okay"; + + flash1: flash@0 { + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "user"; + reg = <0x00000000 0x00200000>; + }; + }; + }; +}; + &pci0 { pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; @@ -266,6 +292,11 @@ function = "i2c2"; }; + msiof0_pins: msiof0 { + groups = "msiof0_clk", "msiof0_tx", "msiof0_rx"; + function = "msiof0"; + }; + scifa2_pins: scifa2 { groups = "scifa2_data_c"; function = "scifa2"; -- 2.17.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH 2/4] ARM: dts: r8a7742-iwg21d-q7: Add SPI NOR support 2020-08-25 16:27 ` [PATCH 2/4] ARM: dts: r8a7742-iwg21d-q7: Add SPI NOR support Lad Prabhakar @ 2020-09-03 11:59 ` Geert Uytterhoeven 2020-09-04 17:24 ` Lad, Prabhakar 0 siblings, 1 reply; 19+ messages in thread From: Geert Uytterhoeven @ 2020-09-03 11:59 UTC (permalink / raw) To: Lad Prabhakar Cc: Magnus Damm, Rob Herring, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, Prabhakar Hi Prabhakar, On Tue, Aug 25, 2020 at 6:28 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Add support for the SPI NOR device which is connected to MSIOF0 interface > on the iWave RainboW-G21d-q7 board. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> > --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > @@ -220,6 +220,32 @@ > status = "okay"; > }; > > +&msiof0 { > + pinctrl-0 = <&msiof0_pins>; > + pinctrl-names = "default"; > + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; > + > + status = "okay"; > + > + flash1: flash@0 { > + compatible = "sst,sst25vf016b", "jedec,spi-nor"; > + reg = <0>; > + spi-max-frequency = <50000000>; > + m25p,fast-read; > + > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + partition@0 { > + label = "user"; > + reg = <0x00000000 0x00200000>; > + }; > + }; > + }; > +}; > + > &pci0 { > pinctrl-0 = <&usb0_pins>; > pinctrl-names = "default"; > @@ -266,6 +292,11 @@ > function = "i2c2"; > }; > > + msiof0_pins: msiof0 { > + groups = "msiof0_clk", "msiof0_tx", "msiof0_rx"; I think you're missing "msiof0_sync", connected to SPI_CS0#? With that fixed: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > + function = "msiof0"; > + }; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/4] ARM: dts: r8a7742-iwg21d-q7: Add SPI NOR support 2020-09-03 11:59 ` Geert Uytterhoeven @ 2020-09-04 17:24 ` Lad, Prabhakar 0 siblings, 0 replies; 19+ messages in thread From: Lad, Prabhakar @ 2020-09-04 17:24 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List Hi Geert, Thank you for the review. On Thu, Sep 3, 2020 at 12:59 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Tue, Aug 25, 2020 at 6:28 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Add support for the SPI NOR device which is connected to MSIOF0 interface > > on the iWave RainboW-G21d-q7 board. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> > > > --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > > +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > > @@ -220,6 +220,32 @@ > > status = "okay"; > > }; > > > > +&msiof0 { > > + pinctrl-0 = <&msiof0_pins>; > > + pinctrl-names = "default"; > > + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; > > + > > + status = "okay"; > > + > > + flash1: flash@0 { > > + compatible = "sst,sst25vf016b", "jedec,spi-nor"; > > + reg = <0>; > > + spi-max-frequency = <50000000>; > > + m25p,fast-read; > > + > > + partitions { > > + compatible = "fixed-partitions"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + partition@0 { > > + label = "user"; > > + reg = <0x00000000 0x00200000>; > > + }; > > + }; > > + }; > > +}; > > + > > &pci0 { > > pinctrl-0 = <&usb0_pins>; > > pinctrl-names = "default"; > > @@ -266,6 +292,11 @@ > > function = "i2c2"; > > }; > > > > + msiof0_pins: msiof0 { > > + groups = "msiof0_clk", "msiof0_tx", "msiof0_rx"; > > I think you're missing "msiof0_sync", connected to SPI_CS0#? > Agreed will fix that and post a v2. Cheers, Prabhakar > With that fixed: > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > > + function = "msiof0"; > > + }; > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 3/4] ARM: dts: r8a7742-iwg21d-q7: Add can0 support to carrier board 2020-08-25 16:27 [PATCH 0/4] iWave G21D-Q7 enable PCIe, flash, CAN and SD2 LED Lad Prabhakar 2020-08-25 16:27 ` [PATCH 1/4] ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller Lad Prabhakar 2020-08-25 16:27 ` [PATCH 2/4] ARM: dts: r8a7742-iwg21d-q7: Add SPI NOR support Lad Prabhakar @ 2020-08-25 16:27 ` Lad Prabhakar 2020-09-03 12:14 ` Geert Uytterhoeven 2020-08-25 16:27 ` [PATCH 4/4] ARM: dts: r8a7742-iwg21d-q7: Enable SD2 LED indication Lad Prabhakar 3 siblings, 1 reply; 19+ messages in thread From: Lad Prabhakar @ 2020-08-25 16:27 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, linux-renesas-soc, devicetree Cc: linux-kernel, Lad Prabhakar, Prabhakar This patch enables CAN0 interface exposed through connector J20 on the carrier board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> --- arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index e709a132f2f7..070fc9729b39 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -198,6 +198,13 @@ }; }; +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + &cmt0 { status = "okay"; }; @@ -214,6 +221,15 @@ }; }; +&gpio1 { + can-trx-en-gpio{ + gpio-hog; + gpios = <28 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "can-trx-en-gpio"; + }; +}; + &hsusb { pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; @@ -287,6 +303,11 @@ function = "tpu0"; }; + can0_pins: can0 { + groups = "can0_data_d"; + function = "can0"; + }; + i2c2_pins: i2c2 { groups = "i2c2_b"; function = "i2c2"; -- 2.17.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH 3/4] ARM: dts: r8a7742-iwg21d-q7: Add can0 support to carrier board 2020-08-25 16:27 ` [PATCH 3/4] ARM: dts: r8a7742-iwg21d-q7: Add can0 support to carrier board Lad Prabhakar @ 2020-09-03 12:14 ` Geert Uytterhoeven 2020-09-04 17:17 ` Lad, Prabhakar 0 siblings, 1 reply; 19+ messages in thread From: Geert Uytterhoeven @ 2020-09-03 12:14 UTC (permalink / raw) To: Lad Prabhakar Cc: Magnus Damm, Rob Herring, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, Prabhakar Hi Prabhakar, On Tue, Aug 25, 2020 at 6:28 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > This patch enables CAN0 interface exposed through connector J20 on the > carrier board. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> According to my schematics, the CAN port on J20 has its signals named CAN0_[RT]XD on the carrier board, but connected to CAN1[RT]X (GP4_[67]) on the SoM. Or am I looking at the wrong file? > --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > @@ -198,6 +198,13 @@ > }; > }; > > +&can0 { can1 > + pinctrl-0 = <&can0_pins>; can1_pins > + pinctrl-names = "default"; > + > + status = "okay"; > +}; > + > &cmt0 { > status = "okay"; > }; > @@ -287,6 +303,11 @@ > function = "tpu0"; > }; > > + can0_pins: can0 { > + groups = "can0_data_d"; can1_data_b > + function = "can0"; > + }; > + > i2c2_pins: i2c2 { > groups = "i2c2_b"; > function = "i2c2"; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 3/4] ARM: dts: r8a7742-iwg21d-q7: Add can0 support to carrier board 2020-09-03 12:14 ` Geert Uytterhoeven @ 2020-09-04 17:17 ` Lad, Prabhakar 0 siblings, 0 replies; 19+ messages in thread From: Lad, Prabhakar @ 2020-09-04 17:17 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List Hi Geert, Thank you for the review. On Thu, Sep 3, 2020 at 1:14 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Tue, Aug 25, 2020 at 6:28 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > This patch enables CAN0 interface exposed through connector J20 on the > > carrier board. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> > > According to my schematics, the CAN port on J20 has its signals named > CAN0_[RT]XD on the carrier board, but connected to CAN1[RT]X (GP4_[67]) > on the SoM. > > Or am I looking at the wrong file? > You are correct, I misplaced the node from the carrier board, will post a v2. Cheers, Prabhakar > > --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > > +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > > @@ -198,6 +198,13 @@ > > }; > > }; > > > > +&can0 { > > can1 > > > + pinctrl-0 = <&can0_pins>; > > can1_pins > > > + pinctrl-names = "default"; > > + > > + status = "okay"; > > +}; > > + > > &cmt0 { > > status = "okay"; > > }; > > > @@ -287,6 +303,11 @@ > > function = "tpu0"; > > }; > > > > + can0_pins: can0 { > > + groups = "can0_data_d"; > > can1_data_b > > > + function = "can0"; > > + }; > > + > > i2c2_pins: i2c2 { > > groups = "i2c2_b"; > > function = "i2c2"; > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 4/4] ARM: dts: r8a7742-iwg21d-q7: Enable SD2 LED indication 2020-08-25 16:27 [PATCH 0/4] iWave G21D-Q7 enable PCIe, flash, CAN and SD2 LED Lad Prabhakar ` (2 preceding siblings ...) 2020-08-25 16:27 ` [PATCH 3/4] ARM: dts: r8a7742-iwg21d-q7: Add can0 support to carrier board Lad Prabhakar @ 2020-08-25 16:27 ` Lad Prabhakar 2020-09-03 12:20 ` Geert Uytterhoeven 2020-10-09 7:26 ` Pavel Machek 3 siblings, 2 replies; 19+ messages in thread From: Lad Prabhakar @ 2020-08-25 16:27 UTC (permalink / raw) To: Geert Uytterhoeven, Magnus Damm, Rob Herring, linux-renesas-soc, devicetree Cc: linux-kernel, Lad Prabhakar, Prabhakar Add support for LED trigger on SD2 interface. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> --- arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index 070fc9729b39..6d31d2401481 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -63,6 +63,16 @@ enable-gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; }; + leds { + compatible = "gpio-leds"; + + sdhi2_led { + label = "sdio-led"; + gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc1"; + }; + }; + lvds-receiver { compatible = "ti,ds90cf384a", "lvds-decoder"; vcc-supply = <&vcc_3v3_tft1>; -- 2.17.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH 4/4] ARM: dts: r8a7742-iwg21d-q7: Enable SD2 LED indication 2020-08-25 16:27 ` [PATCH 4/4] ARM: dts: r8a7742-iwg21d-q7: Enable SD2 LED indication Lad Prabhakar @ 2020-09-03 12:20 ` Geert Uytterhoeven 2020-09-04 17:15 ` Lad, Prabhakar 2020-10-09 7:26 ` Pavel Machek 1 sibling, 1 reply; 19+ messages in thread From: Geert Uytterhoeven @ 2020-09-03 12:20 UTC (permalink / raw) To: Lad Prabhakar Cc: Magnus Damm, Rob Herring, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, Prabhakar Hi Prabhakar, On Tue, Aug 25, 2020 at 6:28 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Add support for LED trigger on SD2 interface. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> > --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > @@ -63,6 +63,16 @@ > enable-gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; > }; > > + leds { > + compatible = "gpio-leds"; > + > + sdhi2_led { > + label = "sdio-led"; > + gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; GPIO_ACTIVE_HIGH? The LED is driven by an NPN transistor, with the LED between 3.3V and the transistor's collector. > + linux,default-trigger = "mmc1"; > + }; > + }; > + > lvds-receiver { > compatible = "ti,ds90cf384a", "lvds-decoder"; > vcc-supply = <&vcc_3v3_tft1>; With the above fixed: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 4/4] ARM: dts: r8a7742-iwg21d-q7: Enable SD2 LED indication 2020-09-03 12:20 ` Geert Uytterhoeven @ 2020-09-04 17:15 ` Lad, Prabhakar 2020-09-07 7:55 ` Geert Uytterhoeven 0 siblings, 1 reply; 19+ messages in thread From: Lad, Prabhakar @ 2020-09-04 17:15 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List Hi Geert, Thank you for the review. On Thu, Sep 3, 2020 at 1:20 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Tue, Aug 25, 2020 at 6:28 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Add support for LED trigger on SD2 interface. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> > > > --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > > +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > > @@ -63,6 +63,16 @@ > > enable-gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; > > }; > > > > + leds { > > + compatible = "gpio-leds"; > > + > > + sdhi2_led { > > + label = "sdio-led"; > > + gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; > > GPIO_ACTIVE_HIGH? > I did try with GPIO_ACTIVE_HIGH and it didn't work as expected. To make sure I can control the LED through sysfs I deleted the node from DTS and exported the pin GP5_22 (858) and writing the value "out" direction and setting the values 0/1 to value did not toggle the SDIO LED as expected and it stayed OFF all the time. Looks like there is some information missing in the schematics. I did some experiments. I completely removed the SDHI, LED and regulator nodes and booted the system and exported GP1_27 (989) and wrote values 0/1 and this toggled the SDIO_LED. U-boot sets the below, so in u-boot the SDIO_LED is ON: gpio_direction_output(GPIO_GP_1_27, 0); /* power on */ gpio_set_value(GPIO_GP_1_27, 0); gpio_direction_output(GPIO_GP_5_22, 0); /* LED */ gpio_set_value(GPIO_GP_5_22, 1); gpio_direction_output(GPIO_GP_1_8, 0); /* 1: 3.3V, 0: 1.8V*/ gpio_set_value(GPIO_GP_1_8, 1); So in comparison we would need a hog node as below (and with this the LED triggers correctly as expected), &gpio5 { sdio-led-gpio { gpio-hog; gpios = <22 GPIO_ACTIVE_HIGH>; output-high; line-name = "sdio-led-gpio"; }; }; Let me know if you are OK with the above. Looks like the SDIO_PWR is tied up with an SDIO_LED pin and the information is missing from schematics. Cheers, Prabhakar > The LED is driven by an NPN transistor, with the LED between 3.3V and > the transistor's collector. > > > + linux,default-trigger = "mmc1"; > > + }; > > + }; > > + > > lvds-receiver { > > compatible = "ti,ds90cf384a", "lvds-decoder"; > > vcc-supply = <&vcc_3v3_tft1>; > > With the above fixed: > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 4/4] ARM: dts: r8a7742-iwg21d-q7: Enable SD2 LED indication 2020-09-04 17:15 ` Lad, Prabhakar @ 2020-09-07 7:55 ` Geert Uytterhoeven 2020-09-07 15:23 ` Lad, Prabhakar 0 siblings, 1 reply; 19+ messages in thread From: Geert Uytterhoeven @ 2020-09-07 7:55 UTC (permalink / raw) To: Lad, Prabhakar Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List Hi Prabhakar, On Fri, Sep 4, 2020 at 7:15 PM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Thu, Sep 3, 2020 at 1:20 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Tue, Aug 25, 2020 at 6:28 PM Lad Prabhakar > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > Add support for LED trigger on SD2 interface. > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> > > > > > --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > > > +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > > > @@ -63,6 +63,16 @@ > > > enable-gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; > > > }; > > > > > > + leds { > > > + compatible = "gpio-leds"; > > > + > > > + sdhi2_led { > > > + label = "sdio-led"; > > > + gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; > > > > GPIO_ACTIVE_HIGH? > > > > The LED is driven by an NPN transistor, with the LED between 3.3V and > > the transistor's collector. Oops, 3.3V is not VCC_3V3, but SD_3V3, so it is not always-on, but controlled by SDIO_PWR. > I did try with GPIO_ACTIVE_HIGH and it didn't work as expected. To > make sure I can control the LED through sysfs I deleted the node from > DTS and exported the pin GP5_22 (858) and writing the value "out" > direction and setting the values 0/1 to value did not toggle the SDIO > LED as expected and it stayed OFF all the time. Hence when SDIO_PWR is turned off, you cannot control the LED just by toggling GP5_22. > Looks like there is some information missing in the schematics. > > I did some experiments. I completely removed the SDHI, LED and > regulator nodes and booted the system and exported GP1_27 (989) and > wrote values 0/1 and this toggled the SDIO_LED. > > U-boot sets the below, so in u-boot the SDIO_LED is ON: > gpio_direction_output(GPIO_GP_1_27, 0); /* power on */ > gpio_set_value(GPIO_GP_1_27, 0); > gpio_direction_output(GPIO_GP_5_22, 0); /* LED */ > gpio_set_value(GPIO_GP_5_22, 1); > gpio_direction_output(GPIO_GP_1_8, 0); /* 1: 3.3V, 0: 1.8V*/ > gpio_set_value(GPIO_GP_1_8, 1); > > So in comparison we would need a hog node as below (and with this the > LED triggers correctly as expected), > > &gpio5 { > sdio-led-gpio { > gpio-hog; > gpios = <22 GPIO_ACTIVE_HIGH>; > output-high; > line-name = "sdio-led-gpio"; > }; > }; > > Let me know if you are OK with the above. The above means the LED is always lit when SDIO_PWR is enabled. While I agree that's some kind of SD activity indicator, probably it's less fine-grained than using the mmc1 trigger? I assume the mmc1 trigger is only activated when SDIO_PWR is enabled. Are you sure this doesn't work? Perhaps your kernel was missing SD trigger support, or "mmc1" is the wrong SD instance? > Looks like the SDIO_PWR is tied up with an SDIO_LED pin and the > information is missing from schematics. No, I think we just misread the schematics. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 4/4] ARM: dts: r8a7742-iwg21d-q7: Enable SD2 LED indication 2020-09-07 7:55 ` Geert Uytterhoeven @ 2020-09-07 15:23 ` Lad, Prabhakar 0 siblings, 0 replies; 19+ messages in thread From: Lad, Prabhakar @ 2020-09-07 15:23 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Linux-Renesas, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List Hi Geert, On Mon, Sep 7, 2020 at 8:55 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Fri, Sep 4, 2020 at 7:15 PM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > On Thu, Sep 3, 2020 at 1:20 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > > On Tue, Aug 25, 2020 at 6:28 PM Lad Prabhakar > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > > Add support for LED trigger on SD2 interface. > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> > > > > > > > --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > > > > +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > > > > @@ -63,6 +63,16 @@ > > > > enable-gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; > > > > }; > > > > > > > > + leds { > > > > + compatible = "gpio-leds"; > > > > + > > > > + sdhi2_led { > > > > + label = "sdio-led"; > > > > + gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; > > > > > > GPIO_ACTIVE_HIGH? > > > > > > The LED is driven by an NPN transistor, with the LED between 3.3V and > > > the transistor's collector. > > Oops, 3.3V is not VCC_3V3, but SD_3V3, so it is not always-on, but > controlled by SDIO_PWR. > > > I did try with GPIO_ACTIVE_HIGH and it didn't work as expected. To > > make sure I can control the LED through sysfs I deleted the node from > > DTS and exported the pin GP5_22 (858) and writing the value "out" > > direction and setting the values 0/1 to value did not toggle the SDIO > > LED as expected and it stayed OFF all the time. > > Hence when SDIO_PWR is turned off, you cannot control the LED just by > toggling GP5_22. > > > Looks like there is some information missing in the schematics. > > > > I did some experiments. I completely removed the SDHI, LED and > > regulator nodes and booted the system and exported GP1_27 (989) and > > wrote values 0/1 and this toggled the SDIO_LED. > > > > U-boot sets the below, so in u-boot the SDIO_LED is ON: > > gpio_direction_output(GPIO_GP_1_27, 0); /* power on */ > > gpio_set_value(GPIO_GP_1_27, 0); > > gpio_direction_output(GPIO_GP_5_22, 0); /* LED */ > > gpio_set_value(GPIO_GP_5_22, 1); > > gpio_direction_output(GPIO_GP_1_8, 0); /* 1: 3.3V, 0: 1.8V*/ > > gpio_set_value(GPIO_GP_1_8, 1); > > > > So in comparison we would need a hog node as below (and with this the > > LED triggers correctly as expected), > > > > &gpio5 { > > sdio-led-gpio { > > gpio-hog; > > gpios = <22 GPIO_ACTIVE_HIGH>; > > output-high; > > line-name = "sdio-led-gpio"; > > }; > > }; > > > > Let me know if you are OK with the above. > > The above means the LED is always lit when SDIO_PWR is enabled. > While I agree that's some kind of SD activity indicator, probably it's less > fine-grained than using the mmc1 trigger? > I assume the mmc1 trigger is only activated when SDIO_PWR is enabled. > Are you sure this doesn't work? > Perhaps your kernel was missing SD trigger support, or "mmc1" is the > wrong SD instance? > > > Looks like the SDIO_PWR is tied up with an SDIO_LED pin and the > > information is missing from schematics. > > No, I think we just misread the schematics. > My bad I misinterpreted the trigger, with GP5_22 being GPIO_ACTIVE_LOW the LED remained ON when the card was inserted and turned OFF when the card was pulled out. When GP5_22 being GPIO_ACTIVE_HIGH the LED blinked and stayed OFF when the card was inserted and remained OFF when the card was pulled out. As a result I misinterpreted it. I can confirm when GP5_22 is GPIO_ACTIVE_HIGH and there is any activity on SD (read/write) the led turns ON. Cheers, Prabhakar ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 4/4] ARM: dts: r8a7742-iwg21d-q7: Enable SD2 LED indication 2020-08-25 16:27 ` [PATCH 4/4] ARM: dts: r8a7742-iwg21d-q7: Enable SD2 LED indication Lad Prabhakar 2020-09-03 12:20 ` Geert Uytterhoeven @ 2020-10-09 7:26 ` Pavel Machek 1 sibling, 0 replies; 19+ messages in thread From: Pavel Machek @ 2020-10-09 7:26 UTC (permalink / raw) To: Lad Prabhakar Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, linux-renesas-soc, devicetree, linux-kernel, Prabhakar [-- Attachment #1: Type: text/plain, Size: 627 bytes --] Hi! > --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts > @@ -63,6 +63,16 @@ > enable-gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; > }; > > + leds { > + compatible = "gpio-leds"; > + > + sdhi2_led { > + label = "sdio-led"; I believe this should be something like "mmc1:green:activity"... > + gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; > + linux,default-trigger = "mmc1"; > + }; > + }; Best regards, Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 181 bytes --] ^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2020-10-09 9:01 UTC | newest] Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-08-25 16:27 [PATCH 0/4] iWave G21D-Q7 enable PCIe, flash, CAN and SD2 LED Lad Prabhakar 2020-08-25 16:27 ` [PATCH 1/4] ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller Lad Prabhakar 2020-09-03 10:18 ` Geert Uytterhoeven 2020-09-03 11:18 ` Lad, Prabhakar 2020-09-03 11:29 ` Geert Uytterhoeven 2020-10-09 7:23 ` Pavel Machek 2020-10-09 9:01 ` Lad, Prabhakar 2020-08-25 16:27 ` [PATCH 2/4] ARM: dts: r8a7742-iwg21d-q7: Add SPI NOR support Lad Prabhakar 2020-09-03 11:59 ` Geert Uytterhoeven 2020-09-04 17:24 ` Lad, Prabhakar 2020-08-25 16:27 ` [PATCH 3/4] ARM: dts: r8a7742-iwg21d-q7: Add can0 support to carrier board Lad Prabhakar 2020-09-03 12:14 ` Geert Uytterhoeven 2020-09-04 17:17 ` Lad, Prabhakar 2020-08-25 16:27 ` [PATCH 4/4] ARM: dts: r8a7742-iwg21d-q7: Enable SD2 LED indication Lad Prabhakar 2020-09-03 12:20 ` Geert Uytterhoeven 2020-09-04 17:15 ` Lad, Prabhakar 2020-09-07 7:55 ` Geert Uytterhoeven 2020-09-07 15:23 ` Lad, Prabhakar 2020-10-09 7:26 ` Pavel Machek
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