From: Alan Tull <atull@kernel.org>
To: Wu Hao <hao.wu@intel.com>
Cc: Moritz Fischer <mdf@kernel.org>,
linux-fpga@vger.kernel.org,
linux-kernel <linux-kernel@vger.kernel.org>,
linux-api@vger.kernel.org, "Kang, Luwei" <luwei.kang@intel.com>,
"Zhang, Yi Z" <yi.z.zhang@intel.com>,
Tim Whisonant <tim.whisonant@intel.com>,
Enno Luebbers <enno.luebbers@intel.com>,
Shiva Rao <shiva.rao@intel.com>,
Christopher Rauer <christopher.rauer@intel.com>,
Xiao Guangrong <guangrong.xiao@linux.intel.com>
Subject: Re: [PATCH v3 09/21] fpga: intel-dfl-pci: add enumeration for feature devices
Date: Thu, 7 Dec 2017 15:41:41 -0600 [thread overview]
Message-ID: <CANk1AXQ3+Y6De1i6i0YacUxS+vBzhEfRX_jJ_wQKJOCWmYetxw@mail.gmail.com> (raw)
In-Reply-To: <1511764948-20972-10-git-send-email-hao.wu@intel.com>
On Mon, Nov 27, 2017 at 12:42 AM, Wu Hao <hao.wu@intel.com> wrote:
> +/* enumerate feature devices under pci device */
> +static int cci_enumerate_feature_devs(struct pci_dev *pcidev)
> +{
> + struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
> + struct fpga_cdev *cdev;
> + struct fpga_enum_info *info;
> + resource_size_t start, len;
> + void __iomem *base;
> + int port_num, bar, i, ret = 0;
> + u32 offset;
> + u64 v;
> +
> + /* allocate enumeration info via pci_dev */
> + info = fpga_enum_info_alloc(&pcidev->dev);
> + if (!info)
> + return -ENOMEM;
> +
> + /* start to find Device Feature List from Bar 0 */
> + base = cci_pci_ioremap_bar(pcidev, 0);
> + if (!base) {
> + ret = -ENOMEM;
> + goto enum_info_free_exit;
> + }
> +
> + /*
> + * PF device has FME and Ports/AFUs, and VF device only has 1 Port/AFU.
> + * check them and add related "Device Feature List" info for the next
> + * step enumeration.
> + */
> + if (feature_is_fme(base)) {
> + start = pci_resource_start(pcidev, 0);
> + len = pci_resource_len(pcidev, 0);
> +
> + fpga_enum_info_add_dfl(info, start, len, base);
> +
> + /*
> + * find more Device Feature Lists (e.g Ports) per information
> + * indicated by FME module.
> + */
> + v = readq(base + FME_HDR_CAP);
> + port_num = FIELD_GET(FME_CAP_NUM_PORTS, v);
> +
> + WARN_ON(port_num > MAX_FPGA_PORT_NUM);
> +
> + for (i = 0; i < port_num; i++) {
> + v = readq(base + FME_HDR_PORT_OFST(i));
> +
> + /* skip ports which are not implemented. */
> + if (!(v & FME_PORT_OFST_IMP))
> + continue;
> +
> + /*
> + * add Port's Device Feature List information for next
> + * step enumeration.
> + */
> + bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
> + offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
> + base = cci_pci_ioremap_bar(pcidev, bar);
> + if (!base)
> + continue;
> +
> + start = pci_resource_start(pcidev, bar) + offset;
> + len = pci_resource_len(pcidev, bar) - offset;
> +
> + fpga_enum_info_add_dfl(info, start, len, base + offset);
> + }
> + } else if (feature_is_port(base)) {
> + start = pci_resource_start(pcidev, 0);
> + len = pci_resource_len(pcidev, 0);
> +
> + fpga_enum_info_add_dfl(info, start, len, base);
> + } else {
> + ret = -ENODEV;
> + goto enum_info_free_exit;
> + }
> +
> + /* start enumeration with prepared enumeration information */
> + cdev = fpga_enumerate_feature_devs(info);
Hi Hao,
I appreciate you separating the DFL enumeration code from this PCIe
module. This made the pcie part quite small. It should work for
embedded platforms just by adding a platform device whose function is
to find the DFL structures at some address and then call these same
fpga_enum_info_add_dfl adn fpga_enumerate_feature_devs functions.
Alan
> + if (IS_ERR(cdev)) {
> + dev_err(&pcidev->dev, "Enumeration failure\n");
> + ret = PTR_ERR(cdev);
> + goto enum_info_free_exit;
> + }
> +
> + drvdata->cdev = cdev;
> +
> +enum_info_free_exit:
> + fpga_enum_info_free(info);
> +
> + return ret;
> +}
> +
> static
> int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid)
> {
> @@ -84,9 +264,22 @@ int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid)
> goto release_region_exit;
> }
>
> - /* TODO: create and add the platform device per feature list */
> - return 0;
> + ret = cci_init_drvdata(pcidev);
> + if (ret) {
> + dev_err(&pcidev->dev, "Fail to init drvdata %d.\n", ret);
> + goto release_region_exit;
> + }
> +
> + ret = cci_enumerate_feature_devs(pcidev);
> + if (ret) {
> + dev_err(&pcidev->dev, "enumeration failure %d.\n", ret);
> + goto remove_drvdata_exit;
> + }
> +
> + return ret;
>
> +remove_drvdata_exit:
> + cci_remove_drvdata(pcidev);
> release_region_exit:
> pci_release_regions(pcidev);
> disable_error_report_exit:
> @@ -97,6 +290,8 @@ int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid)
>
> static void cci_pci_remove(struct pci_dev *pcidev)
> {
> + cci_remove_feature_devs(pcidev);
> + cci_remove_drvdata(pcidev);
> pci_release_regions(pcidev);
> pci_disable_pcie_error_reporting(pcidev);
> pci_disable_device(pcidev);
> --
> 1.8.3.1
>
next prev parent reply other threads:[~2017-12-07 21:42 UTC|newest]
Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-27 6:42 [PATCH v3 00/21] Intel FPGA Device Drivers Wu Hao
2017-11-27 6:42 ` [PATCH v3 01/21] docs: fpga: add a document for Intel FPGA driver overview Wu Hao
2017-12-04 19:55 ` Alan Tull
2017-12-05 3:57 ` Wu Hao
2017-12-06 10:04 ` David Laight
2017-12-20 22:31 ` Alan Tull
2017-12-21 6:02 ` Wu Hao
2017-11-27 6:42 ` [PATCH v3 02/21] fpga: mgr: add region_id to fpga_image_info Wu Hao
2017-11-29 6:11 ` Moritz Fischer
2017-12-04 20:26 ` Alan Tull
2017-12-05 3:36 ` Wu Hao
2018-01-31 15:35 ` Alan Tull
2018-02-01 5:05 ` Wu Hao
2017-11-27 6:42 ` [PATCH v3 03/21] fpga: mgr: add status for fpga-manager Wu Hao
2017-12-04 20:55 ` Alan Tull
2017-12-05 4:08 ` Wu Hao
2017-12-12 18:18 ` Alan Tull
2017-12-13 4:48 ` Wu Hao
2017-11-27 6:42 ` [PATCH v3 04/21] fpga: add device feature list support Wu Hao
2017-11-29 6:07 ` Moritz Fischer
2017-11-30 5:59 ` Wu Hao
2017-12-20 22:29 ` Alan Tull
2017-12-21 0:58 ` Alan Tull
2017-12-21 7:22 ` Wu Hao
2017-12-22 8:45 ` Wu Hao
2018-01-31 23:22 ` Alan Tull
2017-11-27 6:42 ` [PATCH v3 05/21] fpga: dfl: add chardev support for feature devices Wu Hao
2017-11-27 6:42 ` [PATCH v3 06/21] fpga: dfl: adds fpga_cdev_find_port Wu Hao
2018-02-05 22:08 ` Alan Tull
2018-02-06 2:37 ` Wu Hao
2017-11-27 6:42 ` [PATCH v3 07/21] fpga: dfl: add feature device infrastructure Wu Hao
2017-11-27 6:42 ` [PATCH v3 08/21] fpga: add Intel FPGA DFL PCIe device Wu Hao
2017-11-27 10:28 ` David Laight
2017-11-28 3:15 ` Wu Hao
2017-12-04 19:46 ` Alan Tull
2017-12-05 3:33 ` Wu Hao
2017-12-05 17:00 ` Alan Tull
2017-12-06 5:30 ` Wu Hao
2017-12-06 9:44 ` David Laight
2017-12-06 15:29 ` Alan Tull
2017-12-06 16:28 ` David Laight
2017-12-06 22:39 ` Alan Tull
2018-02-01 21:59 ` Alan Tull
2018-02-13 9:36 ` Wu Hao
2017-12-06 9:34 ` David Laight
2017-12-07 3:47 ` Wu Hao
2017-12-06 9:31 ` David Laight
2017-11-27 6:42 ` [PATCH v3 09/21] fpga: intel-dfl-pci: add enumeration for feature devices Wu Hao
2017-12-07 21:41 ` Alan Tull [this message]
2017-12-08 9:25 ` Wu Hao
2017-11-27 6:42 ` [PATCH v3 10/21] fpga: dfl: add FPGA Management Engine driver basic framework Wu Hao
2017-11-27 6:42 ` [PATCH v3 11/21] fpga: dfl: fme: add header sub feature support Wu Hao
2018-02-12 16:51 ` Alan Tull
2018-02-13 3:44 ` Wu Hao
2017-11-27 6:42 ` [PATCH v3 12/21] fpga: dfl: fme: add FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao
2018-01-31 15:31 ` Alan Tull
2018-02-01 5:11 ` Wu Hao
2018-02-01 15:11 ` Moritz Fischer
2017-11-27 6:42 ` [PATCH v3 13/21] fpga: dfl: fme: add partial reconfiguration sub feature support Wu Hao
2017-11-27 6:42 ` [PATCH v3 14/21] fpga: dfl: add fpga manager platform driver for FME Wu Hao
2018-02-01 22:00 ` Alan Tull
2018-02-02 9:42 ` Wu Hao
2018-02-03 0:26 ` Luebbers, Enno
2018-02-03 10:41 ` Moritz Fischer
2018-02-04 10:05 ` Wu Hao
2018-02-05 17:21 ` Alan Tull
2018-02-06 2:17 ` Wu Hao
2018-02-06 4:25 ` Alan Tull
2018-02-06 5:23 ` Wu Hao
2018-02-06 6:44 ` Moritz Fischer
2018-02-04 9:37 ` Wu Hao
2018-02-05 18:36 ` Luebbers, Enno
2018-02-06 1:47 ` Wu Hao
2018-02-06 4:25 ` Alan Tull
2018-02-06 6:47 ` Wu Hao
2018-02-06 18:53 ` Alan Tull
2018-02-07 4:52 ` Wu Hao
2018-02-07 22:37 ` Alan Tull
2017-11-27 6:42 ` [PATCH v3 15/21] fpga: dfl: add fpga bridge " Wu Hao
2018-01-31 15:16 ` Alan Tull
2018-02-01 5:15 ` Wu Hao
2018-02-01 15:11 ` Moritz Fischer
2017-11-27 6:42 ` [PATCH v3 16/21] fpga: dfl: add fpga region " Wu Hao
2018-01-31 20:46 ` Alan Tull
2018-02-01 5:23 ` Wu Hao
2018-02-01 15:13 ` Moritz Fischer
2017-11-27 6:42 ` [PATCH v3 17/21] fpga: dfl: add FPGA Accelerated Function Unit driver basic framework Wu Hao
2017-11-27 6:42 ` [PATCH v3 18/21] fpga: dfl: afu: add header sub feature support Wu Hao
2018-02-12 17:43 ` Alan Tull
2018-02-13 3:33 ` Wu Hao
2017-11-27 6:42 ` [PATCH v3 19/21] fpga: dfl: afu: add FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao
2018-01-31 14:52 ` Alan Tull
2018-02-01 5:16 ` Wu Hao
2018-02-01 15:13 ` Moritz Fischer
2018-02-02 9:08 ` Wu Hao
2017-11-27 6:42 ` [PATCH v3 20/21] fpga: dfl: afu: add user afu sub feature support Wu Hao
2017-11-27 6:42 ` [PATCH v3 21/21] fpga: dfl: afu: add FPGA_PORT_DMA_MAP/UNMAP ioctls support Wu Hao
2017-11-27 21:26 ` [PATCH v3 00/21] Intel FPGA Device Drivers Alan Tull
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