linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: David Laight <David.Laight@ACULAB.COM>
To: "'Alan Tull'" <atull@kernel.org>
Cc: Wu Hao <hao.wu@intel.com>, "mdf@kernel.org" <mdf@kernel.org>,
	"linux-fpga@vger.kernel.org" <linux-fpga@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-api@vger.kernel.org" <linux-api@vger.kernel.org>,
	"luwei.kang@intel.com" <luwei.kang@intel.com>,
	"yi.z.zhang@intel.com" <yi.z.zhang@intel.com>,
	Tim Whisonant <tim.whisonant@intel.com>,
	"Enno Luebbers" <enno.luebbers@intel.com>,
	Shiva Rao <shiva.rao@intel.com>,
	Christopher Rauer <christopher.rauer@intel.com>,
	Xiao Guangrong <guangrong.xiao@linux.intel.com>
Subject: RE: [PATCH v3 08/21] fpga: add Intel FPGA DFL PCIe device
Date: Wed, 6 Dec 2017 16:28:55 +0000	[thread overview]
Message-ID: <e2b9d86fda904f709158c018a099e19d@AcuMS.aculab.com> (raw)
In-Reply-To: <CANk1AXRFfV9dL+82RcdwRtwTwE9jdE5erZ8q8MUud4z_k6Fn=g@mail.gmail.com>

From: Alan Tull
> Sent: 06 December 2017 15:30
> On Wed, Dec 6, 2017 at 3:44 AM, David Laight <David.Laight@aculab.com> wrote:
> > From: Wu Hao
> >> Sent: 06 December 2017 05:30
> > ...
> >> > Regarding file names, it seems like the files added to drivers/fpga
> >> > could be uniformly named dfl-*.[ch].  Some are fpga-dfl-*.[ch] while
> >> > other are currently dfl-*.[ch] currently.
> >
> > They don't even want to do into a drivers/fgpa directory.
> > Maybe drivers/dfl or drivers/dfl/intel
> 
> It's plugged into the fpga framework in drivers/fpga.  This patchset
> also handles reprogramming the fpga, not just the dfl style
> enumeration.  But your points about this being not just for FPGA are
> interesting to me.  Do you have a use for this that isn't
> FPGA-centric?

That all just seems wrong to me.
If you've managed to invent some common code for reprogramming fpga
I'd have though it would be library functions.

The driver ought to sit somewhere related to its functionality.

Our fpga loads from a serial EEPROM, the image is about 6.5MB.
We can rewrite it from userspace by mmap()ing part of one of the BARs
to access some very locally written (by me) VHDL that does most of
the required bit-banging for 32it word accesses.
You really wouldn't want to load 6.5MB into kernel space!

We also had to solve the problem of 9 separate driver modules that
want to access different parts of the BARs.
I think we have 46 separate slaves in the fpgas BARs (most are in 1 BAR).
Some of these are common between different boards (or completely different
memory maps for the same board.

I can imagine some generic method of having a 'board' driver for a
specific PCI-id that knows the BAR offsets of various functions so that
other sub-drivers could be loaded to access those functions.
But that is some kind of pseudo-bus not fpga specific in any way.

	David

  reply	other threads:[~2017-12-06 16:28 UTC|newest]

Thread overview: 98+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-27  6:42 [PATCH v3 00/21] Intel FPGA Device Drivers Wu Hao
2017-11-27  6:42 ` [PATCH v3 01/21] docs: fpga: add a document for Intel FPGA driver overview Wu Hao
2017-12-04 19:55   ` Alan Tull
2017-12-05  3:57     ` Wu Hao
2017-12-06 10:04     ` David Laight
2017-12-20 22:31   ` Alan Tull
2017-12-21  6:02     ` Wu Hao
2017-11-27  6:42 ` [PATCH v3 02/21] fpga: mgr: add region_id to fpga_image_info Wu Hao
2017-11-29  6:11   ` Moritz Fischer
2017-12-04 20:26     ` Alan Tull
2017-12-05  3:36       ` Wu Hao
2018-01-31 15:35         ` Alan Tull
2018-02-01  5:05           ` Wu Hao
2017-11-27  6:42 ` [PATCH v3 03/21] fpga: mgr: add status for fpga-manager Wu Hao
2017-12-04 20:55   ` Alan Tull
2017-12-05  4:08     ` Wu Hao
2017-12-12 18:18   ` Alan Tull
2017-12-13  4:48     ` Wu Hao
2017-11-27  6:42 ` [PATCH v3 04/21] fpga: add device feature list support Wu Hao
2017-11-29  6:07   ` Moritz Fischer
2017-11-30  5:59     ` Wu Hao
2017-12-20 22:29   ` Alan Tull
2017-12-21  0:58     ` Alan Tull
2017-12-21  7:22       ` Wu Hao
2017-12-22  8:45         ` Wu Hao
2018-01-31 23:22           ` Alan Tull
2017-11-27  6:42 ` [PATCH v3 05/21] fpga: dfl: add chardev support for feature devices Wu Hao
2017-11-27  6:42 ` [PATCH v3 06/21] fpga: dfl: adds fpga_cdev_find_port Wu Hao
2018-02-05 22:08   ` Alan Tull
2018-02-06  2:37     ` Wu Hao
2017-11-27  6:42 ` [PATCH v3 07/21] fpga: dfl: add feature device infrastructure Wu Hao
2017-11-27  6:42 ` [PATCH v3 08/21] fpga: add Intel FPGA DFL PCIe device Wu Hao
2017-11-27 10:28   ` David Laight
2017-11-28  3:15     ` Wu Hao
2017-12-04 19:46       ` Alan Tull
2017-12-05  3:33         ` Wu Hao
2017-12-05 17:00           ` Alan Tull
2017-12-06  5:30             ` Wu Hao
2017-12-06  9:44               ` David Laight
2017-12-06 15:29                 ` Alan Tull
2017-12-06 16:28                   ` David Laight [this message]
2017-12-06 22:39                     ` Alan Tull
2018-02-01 21:59               ` Alan Tull
2018-02-13  9:36                 ` Wu Hao
2017-12-06  9:34           ` David Laight
2017-12-07  3:47             ` Wu Hao
2017-12-06  9:31         ` David Laight
2017-11-27  6:42 ` [PATCH v3 09/21] fpga: intel-dfl-pci: add enumeration for feature devices Wu Hao
2017-12-07 21:41   ` Alan Tull
2017-12-08  9:25     ` Wu Hao
2017-11-27  6:42 ` [PATCH v3 10/21] fpga: dfl: add FPGA Management Engine driver basic framework Wu Hao
2017-11-27  6:42 ` [PATCH v3 11/21] fpga: dfl: fme: add header sub feature support Wu Hao
2018-02-12 16:51   ` Alan Tull
2018-02-13  3:44     ` Wu Hao
2017-11-27  6:42 ` [PATCH v3 12/21] fpga: dfl: fme: add FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao
2018-01-31 15:31   ` Alan Tull
2018-02-01  5:11     ` Wu Hao
2018-02-01 15:11       ` Moritz Fischer
2017-11-27  6:42 ` [PATCH v3 13/21] fpga: dfl: fme: add partial reconfiguration sub feature support Wu Hao
2017-11-27  6:42 ` [PATCH v3 14/21] fpga: dfl: add fpga manager platform driver for FME Wu Hao
2018-02-01 22:00   ` Alan Tull
2018-02-02  9:42     ` Wu Hao
2018-02-03  0:26       ` Luebbers, Enno
2018-02-03 10:41         ` Moritz Fischer
2018-02-04 10:05           ` Wu Hao
2018-02-05 17:21             ` Alan Tull
2018-02-06  2:17               ` Wu Hao
2018-02-06  4:25                 ` Alan Tull
2018-02-06  5:23                   ` Wu Hao
2018-02-06  6:44                   ` Moritz Fischer
2018-02-04  9:37         ` Wu Hao
2018-02-05 18:36           ` Luebbers, Enno
2018-02-06  1:47             ` Wu Hao
2018-02-06  4:25               ` Alan Tull
2018-02-06  6:47                 ` Wu Hao
2018-02-06 18:53                   ` Alan Tull
2018-02-07  4:52                     ` Wu Hao
2018-02-07 22:37                       ` Alan Tull
2017-11-27  6:42 ` [PATCH v3 15/21] fpga: dfl: add fpga bridge " Wu Hao
2018-01-31 15:16   ` Alan Tull
2018-02-01  5:15     ` Wu Hao
2018-02-01 15:11       ` Moritz Fischer
2017-11-27  6:42 ` [PATCH v3 16/21] fpga: dfl: add fpga region " Wu Hao
2018-01-31 20:46   ` Alan Tull
2018-02-01  5:23     ` Wu Hao
2018-02-01 15:13       ` Moritz Fischer
2017-11-27  6:42 ` [PATCH v3 17/21] fpga: dfl: add FPGA Accelerated Function Unit driver basic framework Wu Hao
2017-11-27  6:42 ` [PATCH v3 18/21] fpga: dfl: afu: add header sub feature support Wu Hao
2018-02-12 17:43   ` Alan Tull
2018-02-13  3:33     ` Wu Hao
2017-11-27  6:42 ` [PATCH v3 19/21] fpga: dfl: afu: add FPGA_GET_API_VERSION/CHECK_EXTENSION ioctls support Wu Hao
2018-01-31 14:52   ` Alan Tull
2018-02-01  5:16     ` Wu Hao
2018-02-01 15:13       ` Moritz Fischer
2018-02-02  9:08         ` Wu Hao
2017-11-27  6:42 ` [PATCH v3 20/21] fpga: dfl: afu: add user afu sub feature support Wu Hao
2017-11-27  6:42 ` [PATCH v3 21/21] fpga: dfl: afu: add FPGA_PORT_DMA_MAP/UNMAP ioctls support Wu Hao
2017-11-27 21:26 ` [PATCH v3 00/21] Intel FPGA Device Drivers Alan Tull

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=e2b9d86fda904f709158c018a099e19d@AcuMS.aculab.com \
    --to=david.laight@aculab.com \
    --cc=atull@kernel.org \
    --cc=christopher.rauer@intel.com \
    --cc=enno.luebbers@intel.com \
    --cc=guangrong.xiao@linux.intel.com \
    --cc=hao.wu@intel.com \
    --cc=linux-api@vger.kernel.org \
    --cc=linux-fpga@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=luwei.kang@intel.com \
    --cc=mdf@kernel.org \
    --cc=shiva.rao@intel.com \
    --cc=tim.whisonant@intel.com \
    --cc=yi.z.zhang@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).