* [PATCH v4 0/2] mmc: sdhci: export sdhci_execute_tuning(), then add Cadence SDHCI driver @ 2016-12-05 2:10 Masahiro Yamada 2016-12-05 2:10 ` [PATCH v4 1/2] mmc: sdhci: export sdhci_execute_tuning() Masahiro Yamada 2016-12-05 2:10 ` [PATCH v4 2/2] mmc: sdhci-cadence: add Cadence SD4HC support Masahiro Yamada 0 siblings, 2 replies; 12+ messages in thread From: Masahiro Yamada @ 2016-12-05 2:10 UTC (permalink / raw) To: linux-mmc Cc: Adrian Hunter, Ulf Hansson, Masahiro Yamada, Douglas Anderson, devicetree, Al Cooper, linux-kernel, Stefan Wahren, Rob Herring, Andrei Pistirica, Wolfram Sang, Joshua Henderson, Mark Rutland, Simon Horman, Eric Anholt 1/2 exports sdhci_execute_tuning(), which I want to use for 2/2. 2/2 adds a new driver for Cadence's controller IP. Masahiro Yamada (2): mmc: sdhci: export sdhci_execute_tuning() mmc: sdhci-cadence: add Cadence SD4HC support .../devicetree/bindings/mmc/sdhci-cadence.txt | 30 +++ drivers/mmc/host/Kconfig | 11 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-cadence.c | 280 +++++++++++++++++++++ drivers/mmc/host/sdhci.c | 3 +- drivers/mmc/host/sdhci.h | 1 + 6 files changed, 325 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-cadence.txt create mode 100644 drivers/mmc/host/sdhci-cadence.c -- 2.7.4 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 1/2] mmc: sdhci: export sdhci_execute_tuning() 2016-12-05 2:10 [PATCH v4 0/2] mmc: sdhci: export sdhci_execute_tuning(), then add Cadence SDHCI driver Masahiro Yamada @ 2016-12-05 2:10 ` Masahiro Yamada 2016-12-08 11:49 ` Adrian Hunter 2016-12-08 12:31 ` Ulf Hansson 2016-12-05 2:10 ` [PATCH v4 2/2] mmc: sdhci-cadence: add Cadence SD4HC support Masahiro Yamada 1 sibling, 2 replies; 12+ messages in thread From: Masahiro Yamada @ 2016-12-05 2:10 UTC (permalink / raw) To: linux-mmc; +Cc: Adrian Hunter, Ulf Hansson, Masahiro Yamada, linux-kernel Some SDHCI-compat controllers support not only SD, but also eMMC, but they use different commands for tuning: CMD19 for SD, CMD21 for eMMC. Due to the difference of the underlying mechanism, some controllers (at least, the Cadence IP is the case) provide their own registers for the eMMC tuning. This commit will be useful when we want to override .execute_tuning callback (for eMMC HS200 tuning), but still let it fall back to sdhci_execute_tuning() for SD timing. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> --- I want to use this in the next commit. The Cadence IP supports eMMC as well as SD. I want to re-use the sdhci_execute_tuning() for SD timing. On the other hand, Cadence provides its own way for eMMC HS200 tuning; I need to touch some registers that are specific to Cadence's design. Changes in v4: - export sdhci_execute_tuning() instead of using execute_execute_tuning() Changes in v3: None Changes in v2: None drivers/mmc/host/sdhci.c | 3 ++- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 42ef3eb..0c03a89 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1948,7 +1948,7 @@ static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) return 0; } -static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) +int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) { struct sdhci_host *host = mmc_priv(mmc); u16 ctrl; @@ -2141,6 +2141,7 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) spin_unlock_irqrestore(&host->lock, flags); return err; } +EXPORT_SYMBOL_GPL(sdhci_execute_tuning); static int sdhci_select_drive_strength(struct mmc_card *card, unsigned int max_dtr, int host_drv, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 9c35776..786eee9 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -689,6 +689,7 @@ void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, void sdhci_set_bus_width(struct sdhci_host *host, int width); void sdhci_reset(struct sdhci_host *host, u8 mask); void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); +int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); #ifdef CONFIG_PM extern int sdhci_suspend_host(struct sdhci_host *host); -- 2.7.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v4 1/2] mmc: sdhci: export sdhci_execute_tuning() 2016-12-05 2:10 ` [PATCH v4 1/2] mmc: sdhci: export sdhci_execute_tuning() Masahiro Yamada @ 2016-12-08 11:49 ` Adrian Hunter 2016-12-08 11:53 ` Adrian Hunter 2016-12-08 12:31 ` Ulf Hansson 1 sibling, 1 reply; 12+ messages in thread From: Adrian Hunter @ 2016-12-08 11:49 UTC (permalink / raw) To: Masahiro Yamada, linux-mmc; +Cc: Ulf Hansson, linux-kernel On 05/12/16 04:10, Masahiro Yamada wrote: > Some SDHCI-compat controllers support not only SD, but also eMMC, > but they use different commands for tuning: CMD19 for SD, CMD21 for > eMMC. > > Due to the difference of the underlying mechanism, some controllers > (at least, the Cadence IP is the case) provide their own registers > for the eMMC tuning. > > This commit will be useful when we want to override .execute_tuning > callback (for eMMC HS200 tuning), but still let it fall back to > sdhci_execute_tuning() for SD timing. > > Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Adrian Hunter <adrian.hunter@intel.com> > --- > > I want to use this in the next commit. > The Cadence IP supports eMMC as well as SD. > > I want to re-use the sdhci_execute_tuning() for SD timing. > > On the other hand, Cadence provides its own way for eMMC HS200 tuning; > I need to touch some registers that are specific to Cadence's design. > > > Changes in v4: > - export sdhci_execute_tuning() instead of using > execute_execute_tuning() > > Changes in v3: None > Changes in v2: None > > drivers/mmc/host/sdhci.c | 3 ++- > drivers/mmc/host/sdhci.h | 1 + > 2 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c > index 42ef3eb..0c03a89 100644 > --- a/drivers/mmc/host/sdhci.c > +++ b/drivers/mmc/host/sdhci.c > @@ -1948,7 +1948,7 @@ static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) > return 0; > } > > -static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) > +int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) > { > struct sdhci_host *host = mmc_priv(mmc); > u16 ctrl; > @@ -2141,6 +2141,7 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) > spin_unlock_irqrestore(&host->lock, flags); > return err; > } > +EXPORT_SYMBOL_GPL(sdhci_execute_tuning); > > static int sdhci_select_drive_strength(struct mmc_card *card, > unsigned int max_dtr, int host_drv, > diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h > index 9c35776..786eee9 100644 > --- a/drivers/mmc/host/sdhci.h > +++ b/drivers/mmc/host/sdhci.h > @@ -689,6 +689,7 @@ void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, > void sdhci_set_bus_width(struct sdhci_host *host, int width); > void sdhci_reset(struct sdhci_host *host, u8 mask); > void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); > +int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); > > #ifdef CONFIG_PM > extern int sdhci_suspend_host(struct sdhci_host *host); > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 1/2] mmc: sdhci: export sdhci_execute_tuning() 2016-12-08 11:49 ` Adrian Hunter @ 2016-12-08 11:53 ` Adrian Hunter 0 siblings, 0 replies; 12+ messages in thread From: Adrian Hunter @ 2016-12-08 11:53 UTC (permalink / raw) To: Masahiro Yamada, linux-mmc; +Cc: Ulf Hansson, linux-kernel On 08/12/16 13:49, Adrian Hunter wrote: > On 05/12/16 04:10, Masahiro Yamada wrote: >> Some SDHCI-compat controllers support not only SD, but also eMMC, >> but they use different commands for tuning: CMD19 for SD, CMD21 for >> eMMC. >> >> Due to the difference of the underlying mechanism, some controllers >> (at least, the Cadence IP is the case) provide their own registers >> for the eMMC tuning. >> >> This commit will be useful when we want to override .execute_tuning >> callback (for eMMC HS200 tuning), but still let it fall back to >> sdhci_execute_tuning() for SD timing. >> >> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> > > Adrian Hunter <adrian.hunter@intel.com> I mean: Acked-by: Adrian Hunter <adrian.hunter@intel.com> > >> --- >> >> I want to use this in the next commit. >> The Cadence IP supports eMMC as well as SD. >> >> I want to re-use the sdhci_execute_tuning() for SD timing. >> >> On the other hand, Cadence provides its own way for eMMC HS200 tuning; >> I need to touch some registers that are specific to Cadence's design. >> >> >> Changes in v4: >> - export sdhci_execute_tuning() instead of using >> execute_execute_tuning() >> >> Changes in v3: None >> Changes in v2: None >> >> drivers/mmc/host/sdhci.c | 3 ++- >> drivers/mmc/host/sdhci.h | 1 + >> 2 files changed, 3 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c >> index 42ef3eb..0c03a89 100644 >> --- a/drivers/mmc/host/sdhci.c >> +++ b/drivers/mmc/host/sdhci.c >> @@ -1948,7 +1948,7 @@ static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) >> return 0; >> } >> >> -static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) >> +int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) >> { >> struct sdhci_host *host = mmc_priv(mmc); >> u16 ctrl; >> @@ -2141,6 +2141,7 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) >> spin_unlock_irqrestore(&host->lock, flags); >> return err; >> } >> +EXPORT_SYMBOL_GPL(sdhci_execute_tuning); >> >> static int sdhci_select_drive_strength(struct mmc_card *card, >> unsigned int max_dtr, int host_drv, >> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h >> index 9c35776..786eee9 100644 >> --- a/drivers/mmc/host/sdhci.h >> +++ b/drivers/mmc/host/sdhci.h >> @@ -689,6 +689,7 @@ void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, >> void sdhci_set_bus_width(struct sdhci_host *host, int width); >> void sdhci_reset(struct sdhci_host *host, u8 mask); >> void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); >> +int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); >> >> #ifdef CONFIG_PM >> extern int sdhci_suspend_host(struct sdhci_host *host); >> > > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 1/2] mmc: sdhci: export sdhci_execute_tuning() 2016-12-05 2:10 ` [PATCH v4 1/2] mmc: sdhci: export sdhci_execute_tuning() Masahiro Yamada 2016-12-08 11:49 ` Adrian Hunter @ 2016-12-08 12:31 ` Ulf Hansson 1 sibling, 0 replies; 12+ messages in thread From: Ulf Hansson @ 2016-12-08 12:31 UTC (permalink / raw) To: Masahiro Yamada; +Cc: linux-mmc, Adrian Hunter, linux-kernel On 5 December 2016 at 03:10, Masahiro Yamada <yamada.masahiro@socionext.com> wrote: > Some SDHCI-compat controllers support not only SD, but also eMMC, > but they use different commands for tuning: CMD19 for SD, CMD21 for > eMMC. > > Due to the difference of the underlying mechanism, some controllers > (at least, the Cadence IP is the case) provide their own registers > for the eMMC tuning. > > This commit will be useful when we want to override .execute_tuning > callback (for eMMC HS200 tuning), but still let it fall back to > sdhci_execute_tuning() for SD timing. > > Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Thanks, applied for next! Kind regards Uffe > --- > > I want to use this in the next commit. > The Cadence IP supports eMMC as well as SD. > > I want to re-use the sdhci_execute_tuning() for SD timing. > > On the other hand, Cadence provides its own way for eMMC HS200 tuning; > I need to touch some registers that are specific to Cadence's design. > > > Changes in v4: > - export sdhci_execute_tuning() instead of using > execute_execute_tuning() > > Changes in v3: None > Changes in v2: None > > drivers/mmc/host/sdhci.c | 3 ++- > drivers/mmc/host/sdhci.h | 1 + > 2 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c > index 42ef3eb..0c03a89 100644 > --- a/drivers/mmc/host/sdhci.c > +++ b/drivers/mmc/host/sdhci.c > @@ -1948,7 +1948,7 @@ static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) > return 0; > } > > -static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) > +int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) > { > struct sdhci_host *host = mmc_priv(mmc); > u16 ctrl; > @@ -2141,6 +2141,7 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) > spin_unlock_irqrestore(&host->lock, flags); > return err; > } > +EXPORT_SYMBOL_GPL(sdhci_execute_tuning); > > static int sdhci_select_drive_strength(struct mmc_card *card, > unsigned int max_dtr, int host_drv, > diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h > index 9c35776..786eee9 100644 > --- a/drivers/mmc/host/sdhci.h > +++ b/drivers/mmc/host/sdhci.h > @@ -689,6 +689,7 @@ void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, > void sdhci_set_bus_width(struct sdhci_host *host, int width); > void sdhci_reset(struct sdhci_host *host, u8 mask); > void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); > +int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); > > #ifdef CONFIG_PM > extern int sdhci_suspend_host(struct sdhci_host *host); > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 2/2] mmc: sdhci-cadence: add Cadence SD4HC support 2016-12-05 2:10 [PATCH v4 0/2] mmc: sdhci: export sdhci_execute_tuning(), then add Cadence SDHCI driver Masahiro Yamada 2016-12-05 2:10 ` [PATCH v4 1/2] mmc: sdhci: export sdhci_execute_tuning() Masahiro Yamada @ 2016-12-05 2:10 ` Masahiro Yamada 2016-12-08 11:53 ` Adrian Hunter 2016-12-08 12:32 ` Ulf Hansson 1 sibling, 2 replies; 12+ messages in thread From: Masahiro Yamada @ 2016-12-05 2:10 UTC (permalink / raw) To: linux-mmc Cc: Adrian Hunter, Ulf Hansson, Masahiro Yamada, Douglas Anderson, devicetree, Al Cooper, linux-kernel, Stefan Wahren, Rob Herring, Andrei Pistirica, Wolfram Sang, Joshua Henderson, Mark Rutland, Simon Horman, Eric Anholt Add a driver for the Cadence SD4HC SD/SDIO/eMMC Controller. For SD, it basically relies on the SDHCI standard code. For eMMC, this driver provides some callbacks to support the hardware part that is specific to this IP design. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> --- Changes in v4: - Override mmc_host_ops.execute_tuning instead of the .platform_execute_tuning implementation Changes in v3: - Remove unneeded explanation about HRS and SRS from DT binding; the offsets to HRS/SRS are fixed for this hardware and this is quite normal, like each hardware has a fixed register view except the register base. The detailed register map is what the driver cares about, so no need to explain it in the binding. Changes in v2: - Remove unnecessary "select MMC_SDHCI_IO_ACCESSORS" .../devicetree/bindings/mmc/sdhci-cadence.txt | 30 +++ drivers/mmc/host/Kconfig | 11 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-cadence.c | 280 +++++++++++++++++++++ 4 files changed, 322 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-cadence.txt create mode 100644 drivers/mmc/host/sdhci-cadence.c diff --git a/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt b/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt new file mode 100644 index 0000000..750374f --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt @@ -0,0 +1,30 @@ +* Cadence SD/SDIO/eMMC Host Controller + +Required properties: +- compatible: should be "cdns,sd4hc". +- reg: offset and length of the register set for the device. +- interrupts: a single interrupt specifier. +- clocks: phandle to the input clock. + +Optional properties: +For eMMC configuration, supported speed modes are not indicated by the SDHCI +Capabilities Register. Instead, the following properties should be specified +if supported. See mmc.txt for details. +- mmc-ddr-1_8v +- mmc-ddr-1_2v +- mmc-hs200-1_8v +- mmc-hs200-1_2v +- mmc-hs400-1_8v +- mmc-hs400-1_2v + +Example: + emmc: sdhci@5a000000 { + compatible = "cdns,sd4hc"; + reg = <0x5a000000 0x400>; + interrupts = <0 78 4>; + clocks = <&clk 4>; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + }; diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index ab9181e..8ac1640 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -164,6 +164,17 @@ config MMC_SDHCI_OF_HLWD If unsure, say N. +config MMC_SDHCI_CADENCE + tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller" + depends on MMC_SDHCI_PLTFM + depends on OF + help + This selects the Cadence SD/SDIO/eMMC driver. + + If you have a controller with this interface, say Y or M here. + + If unsure, say N. + config MMC_SDHCI_CNS3XXX tristate "SDHCI support on the Cavium Networks CNS3xxx SoC" depends on ARCH_CNS3XXX diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index e49a82a..55f7193 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o +obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c new file mode 100644 index 0000000..6e2545f --- /dev/null +++ b/drivers/mmc/host/sdhci-cadence.c @@ -0,0 +1,280 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/bitops.h> +#include <linux/iopoll.h> +#include <linux/module.h> +#include <linux/mmc/host.h> + +#include "sdhci-pltfm.h" + +/* HRS - Host Register Set (specific to Cadence) */ +#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */ +#define SDHCI_CDNS_HRS04_ACK BIT(26) +#define SDHCI_CDNS_HRS04_RD BIT(25) +#define SDHCI_CDNS_HRS04_WR BIT(24) +#define SDHCI_CDNS_HRS04_RDATA_SHIFT 12 +#define SDHCI_CDNS_HRS04_WDATA_SHIFT 8 +#define SDHCI_CDNS_HRS04_ADDR_SHIFT 0 + +#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */ +#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15) +#define SDHCI_CDNS_HRS06_TUNE_SHIFT 8 +#define SDHCI_CDNS_HRS06_TUNE_MASK 0x3f +#define SDHCI_CDNS_HRS06_MODE_MASK 0x7 +#define SDHCI_CDNS_HRS06_MODE_SD 0x0 +#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2 +#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4 +#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5 + +/* SRS - Slot Register Set (SDHCI-compatible) */ +#define SDHCI_CDNS_SRS_BASE 0x200 + +/* PHY */ +#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00 +#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01 +#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02 +#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03 +#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04 +#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05 +#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06 +#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07 +#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08 + +/* + * The tuned val register is 6 bit-wide, but not the whole of the range is + * available. The range 0-42 seems to be available (then 43 wraps around to 0) + * but I am not quite sure if it is official. Use only 0 to 39 for safety. + */ +#define SDHCI_CDNS_MAX_TUNING_LOOP 40 + +struct sdhci_cdns_priv { + void __iomem *hrs_addr; +}; + +static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, + u8 addr, u8 data) +{ + void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04; + u32 tmp; + + tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) | + (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT); + writel(tmp, reg); + + tmp |= SDHCI_CDNS_HRS04_WR; + writel(tmp, reg); + + tmp &= ~SDHCI_CDNS_HRS04_WR; + writel(tmp, reg); +} + +static void sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv) +{ + sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_SD_HS, 4); + sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_SD_DEFAULT, 4); + sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_EMMC_LEGACY, 9); + sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_EMMC_SDR, 2); + sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_EMMC_DDR, 3); +} + +static inline void *sdhci_cdns_priv(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + + return sdhci_pltfm_priv(pltfm_host); +} + +static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host) +{ + /* + * Cadence's spec says the Timeout Clock Frequency is the same as the + * Base Clock Frequency. Divide it by 1000 to return a value in kHz. + */ + return host->max_clk / 1000; +} + +static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + u32 mode, tmp; + + switch (timing) { + case MMC_TIMING_MMC_HS: + mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR; + break; + case MMC_TIMING_MMC_DDR52: + mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR; + break; + case MMC_TIMING_MMC_HS200: + mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200; + break; + case MMC_TIMING_MMC_HS400: + mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400; + break; + default: + mode = SDHCI_CDNS_HRS06_MODE_SD; + break; + } + + /* The speed mode for eMMC is selected by HRS06 register */ + tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06); + tmp &= ~SDHCI_CDNS_HRS06_MODE_MASK; + tmp |= mode; + writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); + + /* For SD, fall back to the default handler */ + if (mode == SDHCI_CDNS_HRS06_MODE_SD) + sdhci_set_uhs_signaling(host, timing); +} + +static const struct sdhci_ops sdhci_cdns_ops = { + .set_clock = sdhci_set_clock, + .get_timeout_clock = sdhci_cdns_get_timeout_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, +}; + +static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = { + .ops = &sdhci_cdns_ops, +}; + +static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06; + u32 tmp; + + if (WARN_ON(val > SDHCI_CDNS_HRS06_TUNE_MASK)) + return -EINVAL; + + tmp = readl(reg); + tmp &= ~(SDHCI_CDNS_HRS06_TUNE_MASK << SDHCI_CDNS_HRS06_TUNE_SHIFT); + tmp |= val << SDHCI_CDNS_HRS06_TUNE_SHIFT; + tmp |= SDHCI_CDNS_HRS06_TUNE_UP; + writel(tmp, reg); + + return readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), + 0, 1); +} + +static int sdhci_cdns_execute_tuning(struct mmc_host *mmc, u32 opcode) +{ + struct sdhci_host *host = mmc_priv(mmc); + int max_streak = 0; + int cur_streak = 0; + int end_of_streak, i; + + /* + * This handler only implements the eMMC tuning that is specific to + * this controller. Fall back to the standard method for SD timing. + */ + if (host->timing != MMC_TIMING_MMC_HS200) + return sdhci_execute_tuning(mmc, opcode); + + if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200)) + return -EINVAL; + + for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) { + if (sdhci_cdns_set_tune_val(host, i) || + mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */ + cur_streak = 0; + } else { /* good */ + cur_streak++; + max_streak = max(max_streak, cur_streak); + end_of_streak = i; + } + } + + if (!max_streak) { + dev_err(mmc_dev(host->mmc), "no tuning point found\n"); + return -EIO; + } + + return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2); +} + +static int sdhci_cdns_probe(struct platform_device *pdev) +{ + struct sdhci_host *host; + struct sdhci_pltfm_host *pltfm_host; + struct sdhci_cdns_priv *priv; + struct clk *clk; + int ret; + + clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = clk_prepare_enable(clk); + if (ret) + return ret; + + host = sdhci_pltfm_init(pdev, &sdhci_cdns_pltfm_data, sizeof(*priv)); + if (IS_ERR(host)) { + ret = PTR_ERR(host); + goto disable_clk; + } + + pltfm_host = sdhci_priv(host); + pltfm_host->clk = clk; + + priv = sdhci_cdns_priv(host); + priv->hrs_addr = host->ioaddr; + host->ioaddr += SDHCI_CDNS_SRS_BASE; + host->mmc_host_ops.execute_tuning = sdhci_cdns_execute_tuning; + + ret = mmc_of_parse(host->mmc); + if (ret) + goto free; + + sdhci_cdns_phy_init(priv); + + ret = sdhci_add_host(host); + if (ret) + goto free; + + return 0; +free: + sdhci_pltfm_free(pdev); +disable_clk: + clk_disable_unprepare(clk); + + return ret; +} + +static const struct of_device_id sdhci_cdns_match[] = { + { .compatible = "cdns,sd4hc" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, sdhci_cdns_match); + +static struct platform_driver sdhci_cdns_driver = { + .driver = { + .name = "sdhci-cdns", + .pm = &sdhci_pltfm_pmops, + .of_match_table = sdhci_cdns_match, + }, + .probe = sdhci_cdns_probe, + .remove = sdhci_pltfm_unregister, +}; +module_platform_driver(sdhci_cdns_driver); + +MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); +MODULE_DESCRIPTION("Cadence SD/SDIO/eMMC Host Controller Driver"); +MODULE_LICENSE("GPL"); -- 2.7.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v4 2/2] mmc: sdhci-cadence: add Cadence SD4HC support 2016-12-05 2:10 ` [PATCH v4 2/2] mmc: sdhci-cadence: add Cadence SD4HC support Masahiro Yamada @ 2016-12-08 11:53 ` Adrian Hunter 2016-12-08 12:32 ` Ulf Hansson 1 sibling, 0 replies; 12+ messages in thread From: Adrian Hunter @ 2016-12-08 11:53 UTC (permalink / raw) To: Masahiro Yamada, linux-mmc Cc: Ulf Hansson, Douglas Anderson, devicetree, Al Cooper, linux-kernel, Stefan Wahren, Rob Herring, Andrei Pistirica, Wolfram Sang, Joshua Henderson, Mark Rutland, Simon Horman, Eric Anholt On 05/12/16 04:10, Masahiro Yamada wrote: > Add a driver for the Cadence SD4HC SD/SDIO/eMMC Controller. > > For SD, it basically relies on the SDHCI standard code. > For eMMC, this driver provides some callbacks to support the > hardware part that is specific to this IP design. > > Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> > --- > > Changes in v4: > - Override mmc_host_ops.execute_tuning instead of the > .platform_execute_tuning implementation > > Changes in v3: > - Remove unneeded explanation about HRS and SRS from DT binding; > the offsets to HRS/SRS are fixed for this hardware and this is > quite normal, like each hardware has a fixed register view except > the register base. The detailed register map is what the driver > cares about, so no need to explain it in the binding. > > Changes in v2: > - Remove unnecessary "select MMC_SDHCI_IO_ACCESSORS" > > .../devicetree/bindings/mmc/sdhci-cadence.txt | 30 +++ > drivers/mmc/host/Kconfig | 11 + > drivers/mmc/host/Makefile | 1 + > drivers/mmc/host/sdhci-cadence.c | 280 +++++++++++++++++++++ > 4 files changed, 322 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-cadence.txt > create mode 100644 drivers/mmc/host/sdhci-cadence.c > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt b/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt > new file mode 100644 > index 0000000..750374f > --- /dev/null > +++ b/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt > @@ -0,0 +1,30 @@ > +* Cadence SD/SDIO/eMMC Host Controller > + > +Required properties: > +- compatible: should be "cdns,sd4hc". > +- reg: offset and length of the register set for the device. > +- interrupts: a single interrupt specifier. > +- clocks: phandle to the input clock. > + > +Optional properties: > +For eMMC configuration, supported speed modes are not indicated by the SDHCI > +Capabilities Register. Instead, the following properties should be specified > +if supported. See mmc.txt for details. > +- mmc-ddr-1_8v > +- mmc-ddr-1_2v > +- mmc-hs200-1_8v > +- mmc-hs200-1_2v > +- mmc-hs400-1_8v > +- mmc-hs400-1_2v > + > +Example: > + emmc: sdhci@5a000000 { > + compatible = "cdns,sd4hc"; > + reg = <0x5a000000 0x400>; > + interrupts = <0 78 4>; > + clocks = <&clk 4>; > + bus-width = <8>; > + mmc-ddr-1_8v; > + mmc-hs200-1_8v; > + mmc-hs400-1_8v; > + }; > diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig > index ab9181e..8ac1640 100644 > --- a/drivers/mmc/host/Kconfig > +++ b/drivers/mmc/host/Kconfig > @@ -164,6 +164,17 @@ config MMC_SDHCI_OF_HLWD > > If unsure, say N. > > +config MMC_SDHCI_CADENCE > + tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller" > + depends on MMC_SDHCI_PLTFM > + depends on OF > + help > + This selects the Cadence SD/SDIO/eMMC driver. > + > + If you have a controller with this interface, say Y or M here. > + > + If unsure, say N. > + > config MMC_SDHCI_CNS3XXX > tristate "SDHCI support on the Cavium Networks CNS3xxx SoC" > depends on ARCH_CNS3XXX > diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile > index e49a82a..55f7193 100644 > --- a/drivers/mmc/host/Makefile > +++ b/drivers/mmc/host/Makefile > @@ -63,6 +63,7 @@ obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o > obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o > > obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o > +obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o > obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o > obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o > obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o > diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c > new file mode 100644 > index 0000000..6e2545f > --- /dev/null > +++ b/drivers/mmc/host/sdhci-cadence.c > @@ -0,0 +1,280 @@ > +/* > + * Copyright (C) 2016 Socionext Inc. > + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/bitops.h> > +#include <linux/iopoll.h> > +#include <linux/module.h> > +#include <linux/mmc/host.h> > + > +#include "sdhci-pltfm.h" > + > +/* HRS - Host Register Set (specific to Cadence) */ > +#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */ > +#define SDHCI_CDNS_HRS04_ACK BIT(26) > +#define SDHCI_CDNS_HRS04_RD BIT(25) > +#define SDHCI_CDNS_HRS04_WR BIT(24) > +#define SDHCI_CDNS_HRS04_RDATA_SHIFT 12 > +#define SDHCI_CDNS_HRS04_WDATA_SHIFT 8 > +#define SDHCI_CDNS_HRS04_ADDR_SHIFT 0 > + > +#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */ > +#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15) > +#define SDHCI_CDNS_HRS06_TUNE_SHIFT 8 > +#define SDHCI_CDNS_HRS06_TUNE_MASK 0x3f > +#define SDHCI_CDNS_HRS06_MODE_MASK 0x7 > +#define SDHCI_CDNS_HRS06_MODE_SD 0x0 > +#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2 > +#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3 > +#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4 > +#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5 > + > +/* SRS - Slot Register Set (SDHCI-compatible) */ > +#define SDHCI_CDNS_SRS_BASE 0x200 > + > +/* PHY */ > +#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00 > +#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01 > +#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02 > +#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03 > +#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04 > +#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05 > +#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06 > +#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07 > +#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08 > + > +/* > + * The tuned val register is 6 bit-wide, but not the whole of the range is > + * available. The range 0-42 seems to be available (then 43 wraps around to 0) > + * but I am not quite sure if it is official. Use only 0 to 39 for safety. > + */ > +#define SDHCI_CDNS_MAX_TUNING_LOOP 40 > + > +struct sdhci_cdns_priv { > + void __iomem *hrs_addr; > +}; > + > +static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, > + u8 addr, u8 data) > +{ > + void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04; > + u32 tmp; > + > + tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) | > + (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT); > + writel(tmp, reg); > + > + tmp |= SDHCI_CDNS_HRS04_WR; > + writel(tmp, reg); > + > + tmp &= ~SDHCI_CDNS_HRS04_WR; > + writel(tmp, reg); > +} > + > +static void sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv) > +{ > + sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_SD_HS, 4); > + sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_SD_DEFAULT, 4); > + sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_EMMC_LEGACY, 9); > + sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_EMMC_SDR, 2); > + sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_EMMC_DDR, 3); > +} > + > +static inline void *sdhci_cdns_priv(struct sdhci_host *host) > +{ > + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > + > + return sdhci_pltfm_priv(pltfm_host); > +} > + > +static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host) > +{ > + /* > + * Cadence's spec says the Timeout Clock Frequency is the same as the > + * Base Clock Frequency. Divide it by 1000 to return a value in kHz. > + */ > + return host->max_clk / 1000; > +} > + > +static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, > + unsigned int timing) > +{ > + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); > + u32 mode, tmp; > + > + switch (timing) { > + case MMC_TIMING_MMC_HS: > + mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR; > + break; > + case MMC_TIMING_MMC_DDR52: > + mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR; > + break; > + case MMC_TIMING_MMC_HS200: > + mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200; > + break; > + case MMC_TIMING_MMC_HS400: > + mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400; > + break; > + default: > + mode = SDHCI_CDNS_HRS06_MODE_SD; > + break; > + } > + > + /* The speed mode for eMMC is selected by HRS06 register */ > + tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06); > + tmp &= ~SDHCI_CDNS_HRS06_MODE_MASK; > + tmp |= mode; > + writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); > + > + /* For SD, fall back to the default handler */ > + if (mode == SDHCI_CDNS_HRS06_MODE_SD) > + sdhci_set_uhs_signaling(host, timing); > +} > + > +static const struct sdhci_ops sdhci_cdns_ops = { > + .set_clock = sdhci_set_clock, > + .get_timeout_clock = sdhci_cdns_get_timeout_clock, > + .set_bus_width = sdhci_set_bus_width, > + .reset = sdhci_reset, > + .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, > +}; > + > +static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = { > + .ops = &sdhci_cdns_ops, > +}; > + > +static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) > +{ > + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); > + void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06; > + u32 tmp; > + > + if (WARN_ON(val > SDHCI_CDNS_HRS06_TUNE_MASK)) > + return -EINVAL; > + > + tmp = readl(reg); > + tmp &= ~(SDHCI_CDNS_HRS06_TUNE_MASK << SDHCI_CDNS_HRS06_TUNE_SHIFT); > + tmp |= val << SDHCI_CDNS_HRS06_TUNE_SHIFT; > + tmp |= SDHCI_CDNS_HRS06_TUNE_UP; > + writel(tmp, reg); > + > + return readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), > + 0, 1); > +} > + > +static int sdhci_cdns_execute_tuning(struct mmc_host *mmc, u32 opcode) > +{ > + struct sdhci_host *host = mmc_priv(mmc); > + int max_streak = 0; > + int cur_streak = 0; > + int end_of_streak, i; > + > + /* > + * This handler only implements the eMMC tuning that is specific to > + * this controller. Fall back to the standard method for SD timing. > + */ > + if (host->timing != MMC_TIMING_MMC_HS200) > + return sdhci_execute_tuning(mmc, opcode); > + > + if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200)) > + return -EINVAL; > + > + for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) { > + if (sdhci_cdns_set_tune_val(host, i) || > + mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */ > + cur_streak = 0; > + } else { /* good */ > + cur_streak++; > + max_streak = max(max_streak, cur_streak); > + end_of_streak = i; > + } > + } > + > + if (!max_streak) { > + dev_err(mmc_dev(host->mmc), "no tuning point found\n"); > + return -EIO; > + } > + > + return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2); > +} > + > +static int sdhci_cdns_probe(struct platform_device *pdev) > +{ > + struct sdhci_host *host; > + struct sdhci_pltfm_host *pltfm_host; > + struct sdhci_cdns_priv *priv; > + struct clk *clk; > + int ret; > + > + clk = devm_clk_get(&pdev->dev, NULL); > + if (IS_ERR(clk)) > + return PTR_ERR(clk); > + > + ret = clk_prepare_enable(clk); > + if (ret) > + return ret; > + > + host = sdhci_pltfm_init(pdev, &sdhci_cdns_pltfm_data, sizeof(*priv)); > + if (IS_ERR(host)) { > + ret = PTR_ERR(host); > + goto disable_clk; > + } > + > + pltfm_host = sdhci_priv(host); > + pltfm_host->clk = clk; > + > + priv = sdhci_cdns_priv(host); > + priv->hrs_addr = host->ioaddr; > + host->ioaddr += SDHCI_CDNS_SRS_BASE; > + host->mmc_host_ops.execute_tuning = sdhci_cdns_execute_tuning; > + > + ret = mmc_of_parse(host->mmc); > + if (ret) > + goto free; > + > + sdhci_cdns_phy_init(priv); > + > + ret = sdhci_add_host(host); > + if (ret) > + goto free; > + > + return 0; > +free: > + sdhci_pltfm_free(pdev); > +disable_clk: > + clk_disable_unprepare(clk); > + > + return ret; > +} > + > +static const struct of_device_id sdhci_cdns_match[] = { > + { .compatible = "cdns,sd4hc" }, > + { /* sentinel */ } > +}; > +MODULE_DEVICE_TABLE(of, sdhci_cdns_match); > + > +static struct platform_driver sdhci_cdns_driver = { > + .driver = { > + .name = "sdhci-cdns", > + .pm = &sdhci_pltfm_pmops, > + .of_match_table = sdhci_cdns_match, > + }, > + .probe = sdhci_cdns_probe, > + .remove = sdhci_pltfm_unregister, > +}; > +module_platform_driver(sdhci_cdns_driver); > + > +MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); > +MODULE_DESCRIPTION("Cadence SD/SDIO/eMMC Host Controller Driver"); > +MODULE_LICENSE("GPL"); > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 2/2] mmc: sdhci-cadence: add Cadence SD4HC support 2016-12-05 2:10 ` [PATCH v4 2/2] mmc: sdhci-cadence: add Cadence SD4HC support Masahiro Yamada 2016-12-08 11:53 ` Adrian Hunter @ 2016-12-08 12:32 ` Ulf Hansson 2016-12-08 12:35 ` Masahiro Yamada 2016-12-08 12:52 ` Masahiro Yamada 1 sibling, 2 replies; 12+ messages in thread From: Ulf Hansson @ 2016-12-08 12:32 UTC (permalink / raw) To: Masahiro Yamada Cc: linux-mmc, Adrian Hunter, Douglas Anderson, devicetree, Al Cooper, linux-kernel, Stefan Wahren, Rob Herring, Andrei Pistirica, Wolfram Sang, Joshua Henderson, Mark Rutland, Simon Horman, Eric Anholt On 5 December 2016 at 03:10, Masahiro Yamada <yamada.masahiro@socionext.com> wrote: > Add a driver for the Cadence SD4HC SD/SDIO/eMMC Controller. > > For SD, it basically relies on the SDHCI standard code. > For eMMC, this driver provides some callbacks to support the > hardware part that is specific to this IP design. > > Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Thanks, applied for next! Kind regards Uffe > --- > > Changes in v4: > - Override mmc_host_ops.execute_tuning instead of the > .platform_execute_tuning implementation > > Changes in v3: > - Remove unneeded explanation about HRS and SRS from DT binding; > the offsets to HRS/SRS are fixed for this hardware and this is > quite normal, like each hardware has a fixed register view except > the register base. The detailed register map is what the driver > cares about, so no need to explain it in the binding. > > Changes in v2: > - Remove unnecessary "select MMC_SDHCI_IO_ACCESSORS" > > .../devicetree/bindings/mmc/sdhci-cadence.txt | 30 +++ > drivers/mmc/host/Kconfig | 11 + > drivers/mmc/host/Makefile | 1 + > drivers/mmc/host/sdhci-cadence.c | 280 +++++++++++++++++++++ > 4 files changed, 322 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-cadence.txt > create mode 100644 drivers/mmc/host/sdhci-cadence.c > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt b/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt > new file mode 100644 > index 0000000..750374f > --- /dev/null > +++ b/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt > @@ -0,0 +1,30 @@ > +* Cadence SD/SDIO/eMMC Host Controller > + > +Required properties: > +- compatible: should be "cdns,sd4hc". > +- reg: offset and length of the register set for the device. > +- interrupts: a single interrupt specifier. > +- clocks: phandle to the input clock. > + > +Optional properties: > +For eMMC configuration, supported speed modes are not indicated by the SDHCI > +Capabilities Register. Instead, the following properties should be specified > +if supported. See mmc.txt for details. > +- mmc-ddr-1_8v > +- mmc-ddr-1_2v > +- mmc-hs200-1_8v > +- mmc-hs200-1_2v > +- mmc-hs400-1_8v > +- mmc-hs400-1_2v > + > +Example: > + emmc: sdhci@5a000000 { > + compatible = "cdns,sd4hc"; > + reg = <0x5a000000 0x400>; > + interrupts = <0 78 4>; > + clocks = <&clk 4>; > + bus-width = <8>; > + mmc-ddr-1_8v; > + mmc-hs200-1_8v; > + mmc-hs400-1_8v; > + }; > diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig > index ab9181e..8ac1640 100644 > --- a/drivers/mmc/host/Kconfig > +++ b/drivers/mmc/host/Kconfig > @@ -164,6 +164,17 @@ config MMC_SDHCI_OF_HLWD > > If unsure, say N. > > +config MMC_SDHCI_CADENCE > + tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller" > + depends on MMC_SDHCI_PLTFM > + depends on OF > + help > + This selects the Cadence SD/SDIO/eMMC driver. > + > + If you have a controller with this interface, say Y or M here. > + > + If unsure, say N. > + > config MMC_SDHCI_CNS3XXX > tristate "SDHCI support on the Cavium Networks CNS3xxx SoC" > depends on ARCH_CNS3XXX > diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile > index e49a82a..55f7193 100644 > --- a/drivers/mmc/host/Makefile > +++ b/drivers/mmc/host/Makefile > @@ -63,6 +63,7 @@ obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o > obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o > > obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o > +obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o > obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o > obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o > obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o > diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c > new file mode 100644 > index 0000000..6e2545f > --- /dev/null > +++ b/drivers/mmc/host/sdhci-cadence.c > @@ -0,0 +1,280 @@ > +/* > + * Copyright (C) 2016 Socionext Inc. > + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/bitops.h> > +#include <linux/iopoll.h> > +#include <linux/module.h> > +#include <linux/mmc/host.h> > + > +#include "sdhci-pltfm.h" > + > +/* HRS - Host Register Set (specific to Cadence) */ > +#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */ > +#define SDHCI_CDNS_HRS04_ACK BIT(26) > +#define SDHCI_CDNS_HRS04_RD BIT(25) > +#define SDHCI_CDNS_HRS04_WR BIT(24) > +#define SDHCI_CDNS_HRS04_RDATA_SHIFT 12 > +#define SDHCI_CDNS_HRS04_WDATA_SHIFT 8 > +#define SDHCI_CDNS_HRS04_ADDR_SHIFT 0 > + > +#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */ > +#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15) > +#define SDHCI_CDNS_HRS06_TUNE_SHIFT 8 > +#define SDHCI_CDNS_HRS06_TUNE_MASK 0x3f > +#define SDHCI_CDNS_HRS06_MODE_MASK 0x7 > +#define SDHCI_CDNS_HRS06_MODE_SD 0x0 > +#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2 > +#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3 > +#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4 > +#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5 > + > +/* SRS - Slot Register Set (SDHCI-compatible) */ > +#define SDHCI_CDNS_SRS_BASE 0x200 > + > +/* PHY */ > +#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00 > +#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01 > +#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02 > +#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03 > +#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04 > +#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05 > +#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06 > +#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07 > +#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08 > + > +/* > + * The tuned val register is 6 bit-wide, but not the whole of the range is > + * available. The range 0-42 seems to be available (then 43 wraps around to 0) > + * but I am not quite sure if it is official. Use only 0 to 39 for safety. > + */ > +#define SDHCI_CDNS_MAX_TUNING_LOOP 40 > + > +struct sdhci_cdns_priv { > + void __iomem *hrs_addr; > +}; > + > +static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, > + u8 addr, u8 data) > +{ > + void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04; > + u32 tmp; > + > + tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) | > + (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT); > + writel(tmp, reg); > + > + tmp |= SDHCI_CDNS_HRS04_WR; > + writel(tmp, reg); > + > + tmp &= ~SDHCI_CDNS_HRS04_WR; > + writel(tmp, reg); > +} > + > +static void sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv) > +{ > + sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_SD_HS, 4); > + sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_SD_DEFAULT, 4); > + sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_EMMC_LEGACY, 9); > + sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_EMMC_SDR, 2); > + sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_EMMC_DDR, 3); > +} > + > +static inline void *sdhci_cdns_priv(struct sdhci_host *host) > +{ > + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > + > + return sdhci_pltfm_priv(pltfm_host); > +} > + > +static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host) > +{ > + /* > + * Cadence's spec says the Timeout Clock Frequency is the same as the > + * Base Clock Frequency. Divide it by 1000 to return a value in kHz. > + */ > + return host->max_clk / 1000; > +} > + > +static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, > + unsigned int timing) > +{ > + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); > + u32 mode, tmp; > + > + switch (timing) { > + case MMC_TIMING_MMC_HS: > + mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR; > + break; > + case MMC_TIMING_MMC_DDR52: > + mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR; > + break; > + case MMC_TIMING_MMC_HS200: > + mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200; > + break; > + case MMC_TIMING_MMC_HS400: > + mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400; > + break; > + default: > + mode = SDHCI_CDNS_HRS06_MODE_SD; > + break; > + } > + > + /* The speed mode for eMMC is selected by HRS06 register */ > + tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06); > + tmp &= ~SDHCI_CDNS_HRS06_MODE_MASK; > + tmp |= mode; > + writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); > + > + /* For SD, fall back to the default handler */ > + if (mode == SDHCI_CDNS_HRS06_MODE_SD) > + sdhci_set_uhs_signaling(host, timing); > +} > + > +static const struct sdhci_ops sdhci_cdns_ops = { > + .set_clock = sdhci_set_clock, > + .get_timeout_clock = sdhci_cdns_get_timeout_clock, > + .set_bus_width = sdhci_set_bus_width, > + .reset = sdhci_reset, > + .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, > +}; > + > +static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = { > + .ops = &sdhci_cdns_ops, > +}; > + > +static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) > +{ > + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); > + void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06; > + u32 tmp; > + > + if (WARN_ON(val > SDHCI_CDNS_HRS06_TUNE_MASK)) > + return -EINVAL; > + > + tmp = readl(reg); > + tmp &= ~(SDHCI_CDNS_HRS06_TUNE_MASK << SDHCI_CDNS_HRS06_TUNE_SHIFT); > + tmp |= val << SDHCI_CDNS_HRS06_TUNE_SHIFT; > + tmp |= SDHCI_CDNS_HRS06_TUNE_UP; > + writel(tmp, reg); > + > + return readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), > + 0, 1); > +} > + > +static int sdhci_cdns_execute_tuning(struct mmc_host *mmc, u32 opcode) > +{ > + struct sdhci_host *host = mmc_priv(mmc); > + int max_streak = 0; > + int cur_streak = 0; > + int end_of_streak, i; > + > + /* > + * This handler only implements the eMMC tuning that is specific to > + * this controller. Fall back to the standard method for SD timing. > + */ > + if (host->timing != MMC_TIMING_MMC_HS200) > + return sdhci_execute_tuning(mmc, opcode); > + > + if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200)) > + return -EINVAL; > + > + for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) { > + if (sdhci_cdns_set_tune_val(host, i) || > + mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */ > + cur_streak = 0; > + } else { /* good */ > + cur_streak++; > + max_streak = max(max_streak, cur_streak); > + end_of_streak = i; > + } > + } > + > + if (!max_streak) { > + dev_err(mmc_dev(host->mmc), "no tuning point found\n"); > + return -EIO; > + } > + > + return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2); > +} > + > +static int sdhci_cdns_probe(struct platform_device *pdev) > +{ > + struct sdhci_host *host; > + struct sdhci_pltfm_host *pltfm_host; > + struct sdhci_cdns_priv *priv; > + struct clk *clk; > + int ret; > + > + clk = devm_clk_get(&pdev->dev, NULL); > + if (IS_ERR(clk)) > + return PTR_ERR(clk); > + > + ret = clk_prepare_enable(clk); > + if (ret) > + return ret; > + > + host = sdhci_pltfm_init(pdev, &sdhci_cdns_pltfm_data, sizeof(*priv)); > + if (IS_ERR(host)) { > + ret = PTR_ERR(host); > + goto disable_clk; > + } > + > + pltfm_host = sdhci_priv(host); > + pltfm_host->clk = clk; > + > + priv = sdhci_cdns_priv(host); > + priv->hrs_addr = host->ioaddr; > + host->ioaddr += SDHCI_CDNS_SRS_BASE; > + host->mmc_host_ops.execute_tuning = sdhci_cdns_execute_tuning; > + > + ret = mmc_of_parse(host->mmc); > + if (ret) > + goto free; > + > + sdhci_cdns_phy_init(priv); > + > + ret = sdhci_add_host(host); > + if (ret) > + goto free; > + > + return 0; > +free: > + sdhci_pltfm_free(pdev); > +disable_clk: > + clk_disable_unprepare(clk); > + > + return ret; > +} > + > +static const struct of_device_id sdhci_cdns_match[] = { > + { .compatible = "cdns,sd4hc" }, > + { /* sentinel */ } > +}; > +MODULE_DEVICE_TABLE(of, sdhci_cdns_match); > + > +static struct platform_driver sdhci_cdns_driver = { > + .driver = { > + .name = "sdhci-cdns", > + .pm = &sdhci_pltfm_pmops, > + .of_match_table = sdhci_cdns_match, > + }, > + .probe = sdhci_cdns_probe, > + .remove = sdhci_pltfm_unregister, > +}; > +module_platform_driver(sdhci_cdns_driver); > + > +MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); > +MODULE_DESCRIPTION("Cadence SD/SDIO/eMMC Host Controller Driver"); > +MODULE_LICENSE("GPL"); > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 2/2] mmc: sdhci-cadence: add Cadence SD4HC support 2016-12-08 12:32 ` Ulf Hansson @ 2016-12-08 12:35 ` Masahiro Yamada 2016-12-08 12:52 ` Masahiro Yamada 1 sibling, 0 replies; 12+ messages in thread From: Masahiro Yamada @ 2016-12-08 12:35 UTC (permalink / raw) To: Ulf Hansson Cc: linux-mmc, Adrian Hunter, Douglas Anderson, devicetree, Al Cooper, linux-kernel, Stefan Wahren, Rob Herring, Andrei Pistirica, Wolfram Sang, Joshua Henderson, Mark Rutland, Simon Horman, Eric Anholt Hi Ulf, 2016-12-08 21:32 GMT+09:00 Ulf Hansson <ulf.hansson@linaro.org>: > On 5 December 2016 at 03:10, Masahiro Yamada > <yamada.masahiro@socionext.com> wrote: >> Add a driver for the Cadence SD4HC SD/SDIO/eMMC Controller. >> >> For SD, it basically relies on the SDHCI standard code. >> For eMMC, this driver provides some callbacks to support the >> hardware part that is specific to this IP design. >> >> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> > > Thanks, applied for next! > > Kind regards > Uffe Please wait. I found a small bug in v4. I will send v5 soon. Thanks. -- Best Regards Masahiro Yamada ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 2/2] mmc: sdhci-cadence: add Cadence SD4HC support 2016-12-08 12:32 ` Ulf Hansson 2016-12-08 12:35 ` Masahiro Yamada @ 2016-12-08 12:52 ` Masahiro Yamada 2016-12-08 14:05 ` Ulf Hansson 1 sibling, 1 reply; 12+ messages in thread From: Masahiro Yamada @ 2016-12-08 12:52 UTC (permalink / raw) To: Ulf Hansson Cc: linux-mmc, Adrian Hunter, Douglas Anderson, devicetree, Al Cooper, linux-kernel, Stefan Wahren, Rob Herring, Andrei Pistirica, Wolfram Sang, Joshua Henderson, Mark Rutland, Simon Horman, Eric Anholt Hi Ulf, 2016-12-08 21:32 GMT+09:00 Ulf Hansson <ulf.hansson@linaro.org>: > On 5 December 2016 at 03:10, Masahiro Yamada > <yamada.masahiro@socionext.com> wrote: >> Add a driver for the Cadence SD4HC SD/SDIO/eMMC Controller. >> >> For SD, it basically relies on the SDHCI standard code. >> For eMMC, this driver provides some callbacks to support the >> hardware part that is specific to this IP design. >> >> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> > > Thanks, applied for next! > Very sorry for my fix at the last minute. I've just posted v5. Please make sure to apply v5. Thanks! -- Best Regards Masahiro Yamada ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 2/2] mmc: sdhci-cadence: add Cadence SD4HC support 2016-12-08 12:52 ` Masahiro Yamada @ 2016-12-08 14:05 ` Ulf Hansson 2016-12-08 16:16 ` Masahiro Yamada 0 siblings, 1 reply; 12+ messages in thread From: Ulf Hansson @ 2016-12-08 14:05 UTC (permalink / raw) To: Masahiro Yamada Cc: linux-mmc, Adrian Hunter, Douglas Anderson, devicetree, Al Cooper, linux-kernel, Stefan Wahren, Rob Herring, Andrei Pistirica, Wolfram Sang, Joshua Henderson, Mark Rutland, Simon Horman, Eric Anholt On 8 December 2016 at 13:52, Masahiro Yamada <yamada.masahiro@socionext.com> wrote: > Hi Ulf, > > 2016-12-08 21:32 GMT+09:00 Ulf Hansson <ulf.hansson@linaro.org>: >> On 5 December 2016 at 03:10, Masahiro Yamada >> <yamada.masahiro@socionext.com> wrote: >>> Add a driver for the Cadence SD4HC SD/SDIO/eMMC Controller. >>> >>> For SD, it basically relies on the SDHCI standard code. >>> For eMMC, this driver provides some callbacks to support the >>> hardware part that is specific to this IP design. >>> >>> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> >> >> Thanks, applied for next! >> > > > Very sorry for my fix at the last minute. > > I've just posted v5. > > Please make sure to apply v5. Okay, I have replaced v4 with v5. Perhaps you should have a look at my next branch to make sure it's all okay. Kind regards Uffe ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 2/2] mmc: sdhci-cadence: add Cadence SD4HC support 2016-12-08 14:05 ` Ulf Hansson @ 2016-12-08 16:16 ` Masahiro Yamada 0 siblings, 0 replies; 12+ messages in thread From: Masahiro Yamada @ 2016-12-08 16:16 UTC (permalink / raw) To: Ulf Hansson Cc: linux-mmc, Adrian Hunter, Douglas Anderson, devicetree, Al Cooper, linux-kernel, Stefan Wahren, Rob Herring, Andrei Pistirica, Wolfram Sang, Joshua Henderson, Mark Rutland, Simon Horman, Eric Anholt Hi Ulf, 2016-12-08 23:05 GMT+09:00 Ulf Hansson <ulf.hansson@linaro.org>: > On 8 December 2016 at 13:52, Masahiro Yamada > <yamada.masahiro@socionext.com> wrote: >> Hi Ulf, >> >> 2016-12-08 21:32 GMT+09:00 Ulf Hansson <ulf.hansson@linaro.org>: >>> On 5 December 2016 at 03:10, Masahiro Yamada >>> <yamada.masahiro@socionext.com> wrote: >>>> Add a driver for the Cadence SD4HC SD/SDIO/eMMC Controller. >>>> >>>> For SD, it basically relies on the SDHCI standard code. >>>> For eMMC, this driver provides some callbacks to support the >>>> hardware part that is specific to this IP design. >>>> >>>> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> >>> >>> Thanks, applied for next! >>> >> >> >> Very sorry for my fix at the last minute. >> >> I've just posted v5. >> >> Please make sure to apply v5. > > Okay, I have replaced v4 with v5. > > Perhaps you should have a look at my next branch to make sure it's all okay. > Yes. Everything looks fine. Thank you! -- Best Regards Masahiro Yamada ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2016-12-08 16:17 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-12-05 2:10 [PATCH v4 0/2] mmc: sdhci: export sdhci_execute_tuning(), then add Cadence SDHCI driver Masahiro Yamada 2016-12-05 2:10 ` [PATCH v4 1/2] mmc: sdhci: export sdhci_execute_tuning() Masahiro Yamada 2016-12-08 11:49 ` Adrian Hunter 2016-12-08 11:53 ` Adrian Hunter 2016-12-08 12:31 ` Ulf Hansson 2016-12-05 2:10 ` [PATCH v4 2/2] mmc: sdhci-cadence: add Cadence SD4HC support Masahiro Yamada 2016-12-08 11:53 ` Adrian Hunter 2016-12-08 12:32 ` Ulf Hansson 2016-12-08 12:35 ` Masahiro Yamada 2016-12-08 12:52 ` Masahiro Yamada 2016-12-08 14:05 ` Ulf Hansson 2016-12-08 16:16 ` Masahiro Yamada
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