From: "S.H. Xie" <shaohui.xie@nxp.com>
To: Marc Zyngier <marc.zyngier@arm.com>,
"shh.xie@gmail.com" <shh.xie@gmail.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
"will.deacon@arm.com" <will.deacon@arm.com>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: Mihai Emilian Bantea <mihai.bantea@nxp.com>,
"C.H. Zhao" <chenhui.zhao@nxp.com>,
"arnd@arndb.de" <arnd@arndb.de>,
"Z.Q. Hou" <zhiqiang.hou@nxp.com>,
"M.H. Lian" <minghuan.lian@nxp.com>,
Vincent Hu <mingkai.hu@nxp.com>,
Horia Geanta Neag <horia.geanta@nxp.com>,
"Q.Y. Gong" <qianyu.gong@nxp.com>
Subject: RE: [PATCH 3/7] [v2] arm64: dts: add QorIQ LS1046A SoC support
Date: Fri, 9 Sep 2016 09:00:26 +0000 [thread overview]
Message-ID: <DB5PR0401MB2183AF1CB29F26B41192F246E8FA0@DB5PR0401MB2183.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <57D1664D.3060502@arm.com>
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_PPI 14 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_PPI 10 IRQ_TYPE_EDGE_RISING>;
>
> No, this is completely wrong. The timer is always level triggered, and you're
> missing the affinity bits that are described the GIC binding.
[S.H] Will use (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW) in next version.
>
> > + };
> > +
> > + pmu {
> > + compatible = "arm,armv8-pmuv3";
>
> Please add "arm,cortex-a72-pmu".
[S.H] Will use "arm,cortex-a72-pmu" in next version.
>
> > + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-affinity = <&cpu0>,
> > + <&cpu1>,
> > + <&cpu2>,
> > + <&cpu3>;
> > + };
> > +
> > + gic: interrupt-controller@1400000 {
> > + compatible = "arm,gic-400";
> > + #interrupt-cells = <3>;
> > + interrupt-controller;
> > + reg = <0x0 0x1410000 0 0x10000>, /* GICD */
> > + <0x0 0x1420000 0 0x20000>, /* GICC */
> > + <0x0 0x1440000 0 0x20000>, /* GICH */
> > + <0x0 0x1460000 0 0x20000>; /* GICV */
> > + interrupts = <1 9 0xf08>;
>
> Please choose between expressing the interrupts entirely with numerals or entirely
> with symbols. At the moment this is a mix between the two.
[S.H] Will fix it in next version.
Thank you!
Shaohui
next prev parent reply other threads:[~2016-09-09 12:32 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-05 10:01 [PATCH 0/7] [v2] arm64: dts: add QorIQ LS1046A SoC and boards support shh.xie
2016-09-05 10:01 ` [PATCH 1/7] [v2] dt-bindings: fsl: updates bindings for some SoC-specific devices shh.xie
2016-09-08 2:30 ` Shawn Guo
2016-09-08 10:57 ` S.H. Xie
2016-09-05 10:01 ` [PATCH 2/7] [v2] dt-bindings: i2c: adds two more nxp devices shh.xie
2016-09-12 16:33 ` Rob Herring
2016-09-05 10:01 ` [PATCH 3/7] [v2] arm64: dts: add QorIQ LS1046A SoC support shh.xie
2016-09-08 13:05 ` Shawn Guo
2016-09-09 6:46 ` S.H. Xie
2016-09-08 13:13 ` Mark Rutland
2016-09-08 13:18 ` Mark Rutland
2016-09-09 6:55 ` S.H. Xie
2016-09-09 9:10 ` Mark Rutland
2016-09-09 9:17 ` S.H. Xie
2016-09-09 6:48 ` S.H. Xie
2016-09-08 13:23 ` Marc Zyngier
2016-09-09 9:00 ` S.H. Xie [this message]
2016-09-05 10:01 ` [PATCH 4/7] [v2] Documentation: DT: Add entry for QorIQ LS1046A-RDB board shh.xie
2016-09-05 10:01 ` [PATCH 5/7] [v2] arm64: dts: add LS1046A-RDB board support shh.xie
2016-09-08 13:12 ` Shawn Guo
2016-09-09 6:44 ` S.H. Xie
2016-09-05 10:01 ` [PATCH 6/7] [v2] Documentation: DT: Add entry for QorIQ LS1046A-QDS board shh.xie
2016-09-05 10:01 ` [PATCH 7/7] [v2] arm64: dts: add LS1046A-QDS board support shh.xie
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