* [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider
@ 2016-09-02 19:07 Stefan Agner
2016-09-05 8:46 ` Meng Yi
0 siblings, 1 reply; 3+ messages in thread
From: Stefan Agner @ 2016-09-02 19:07 UTC (permalink / raw)
To: dri-devel
Cc: meng.yi, alison.wang, jianwei.wang.chn, linux-kernel,
Stefan Agner, stable
Since using clk_register_divider to setup the pixel clock, regmap
is no longer used. Regmap did take care of DCU using different
endianness. Check endianness using the device-tree property
"big-endian" to determine the location of DIV_RATIO.
Cc: stable@vger.kernel.org
Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel clock divider")
Reported-by: Meng Yi <meng.yi@nxp.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 7882387..8dd042e 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -330,6 +330,7 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
const char *pix_clk_in_name;
const struct of_device_id *id;
int ret;
+ u8 div_ratio_shift = 0;
fsl_dev = devm_kzalloc(dev, sizeof(*fsl_dev), GFP_KERNEL);
if (!fsl_dev)
@@ -382,11 +383,15 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
pix_clk_in = fsl_dev->clk;
}
+ if (of_property_read_bool(dev->of_node, "big-endian"))
+ div_ratio_shift = 24;
+
+
pix_clk_in_name = __clk_get_name(pix_clk_in);
snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix", pix_clk_in_name);
fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
pix_clk_in_name, 0, base + DCU_DIV_RATIO,
- 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
+ div_ratio_shift, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
if (IS_ERR(fsl_dev->pix_clk)) {
dev_err(dev, "failed to register pix clk\n");
ret = PTR_ERR(fsl_dev->pix_clk);
--
2.9.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* RE: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider
2016-09-02 19:07 [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider Stefan Agner
@ 2016-09-05 8:46 ` Meng Yi
2016-09-05 19:24 ` Stefan Agner
0 siblings, 1 reply; 3+ messages in thread
From: Meng Yi @ 2016-09-05 8:46 UTC (permalink / raw)
To: Stefan Agner, dri-devel
Cc: alison.wang, jianwei.wang.chn, linux-kernel, stable
> Subject: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider
>
> Since using clk_register_divider to setup the pixel clock, regmap is no longer
> used. Regmap did take care of DCU using different endianness. Check
> endianness using the device-tree property "big-endian" to determine the
> location of DIV_RATIO.
>
> Cc: stable@vger.kernel.org
> Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel
> clock divider")
> Reported-by: Meng Yi <meng.yi@nxp.com>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
> drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-
> dcu/fsl_dcu_drm_drv.c
> index 7882387..8dd042e 100644
> --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
> +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
> @@ -330,6 +330,7 @@ static int fsl_dcu_drm_probe(struct platform_device
> *pdev)
> const char *pix_clk_in_name;
> const struct of_device_id *id;
> int ret;
> + u8 div_ratio_shift = 0;
>
> fsl_dev = devm_kzalloc(dev, sizeof(*fsl_dev), GFP_KERNEL);
> if (!fsl_dev)
> @@ -382,11 +383,15 @@ static int fsl_dcu_drm_probe(struct platform_device
> *pdev)
> pix_clk_in = fsl_dev->clk;
> }
>
> + if (of_property_read_bool(dev->of_node, "big-endian"))
> + div_ratio_shift = 24;
> +
> +
> pix_clk_in_name = __clk_get_name(pix_clk_in);
> snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix",
> pix_clk_in_name);
> fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
> pix_clk_in_name, 0, base + DCU_DIV_RATIO,
> - 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
> + div_ratio_shift, 8, CLK_DIVIDER_ROUND_CLOSEST,
> NULL);
> if (IS_ERR(fsl_dev->pix_clk)) {
> dev_err(dev, "failed to register pix clk\n");
> ret = PTR_ERR(fsl_dev->pix_clk);
> --
> 2.9.0
Tested-by: Meng Yi <meng.yi@nxp.com>
On LS1021A-TWR board.
Meng
^ permalink raw reply [flat|nested] 3+ messages in thread* RE: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider
2016-09-05 8:46 ` Meng Yi
@ 2016-09-05 19:24 ` Stefan Agner
0 siblings, 0 replies; 3+ messages in thread
From: Stefan Agner @ 2016-09-05 19:24 UTC (permalink / raw)
To: Meng Yi; +Cc: dri-devel, alison.wang, jianwei.wang.chn, linux-kernel, stable
On 2016-09-05 01:46, Meng Yi wrote:
>> Subject: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider
>>
>> Since using clk_register_divider to setup the pixel clock, regmap is no longer
>> used. Regmap did take care of DCU using different endianness. Check
>> endianness using the device-tree property "big-endian" to determine the
>> location of DIV_RATIO.
>>
>> Cc: stable@vger.kernel.org
>> Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel
>> clock divider")
>> Reported-by: Meng Yi <meng.yi@nxp.com>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
<snip>
>
> Tested-by: Meng Yi <meng.yi@nxp.com>
> On LS1021A-TWR board.
Thanks, applied!
--
Stefan
^ permalink raw reply [flat|nested] 3+ messages in thread
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2016-09-02 19:07 [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider Stefan Agner
2016-09-05 8:46 ` Meng Yi
2016-09-05 19:24 ` Stefan Agner
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