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From: Rob Herring <robh@kernel.org>
To: Chen-Yu Tsai <wenst@chromium.org>
Cc: Chun-Jie Chen <chun-jie.chen@mediatek.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Nicolas Boichat <drinkcat@chromium.org>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
	<linux-arm-kernel@lists.infradead.org>,
	LKML <linux-kernel@vger.kernel.org>,
	"moderated list:ARM/Mediatek SoC support" 
	<linux-mediatek@lists.infradead.org>,
	linux-clk@vger.kernel.org,
	Devicetree List <devicetree@vger.kernel.org>,
	srv_heupstream <srv_heupstream@mediatek.com>,
	Project_Global_Chrome_Upstream_Group 
	<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: Re: [v2 01/24] dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock
Date: Tue, 24 Aug 2021 09:44:39 -0500	[thread overview]
Message-ID: <YSUF18AZ2HgOnkce@robh.at.kernel.org> (raw)
In-Reply-To: <CAGXv+5FAEFD+dQsZzyZOzmwDDnwLZO3Z8wv8Z-=wVYdjjc3FYg@mail.gmail.com>

On Mon, Aug 23, 2021 at 02:53:34PM +0800, Chen-Yu Tsai wrote:
> Hi,
> 
> On Fri, Aug 20, 2021 at 7:17 PM Chun-Jie Chen
> <chun-jie.chen@mediatek.com> wrote:
> >
> > This patch adds the new binding documentation for system clock
> > and functional clock on Mediatek MT8195.
> >
> > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > ---
> >  .../arm/mediatek/mediatek,mt8195-clock.yaml   | 254 ++++++++++++++++++
> >  .../mediatek/mediatek,mt8195-sys-clock.yaml   |  73 +++++
> >  2 files changed, 327 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> >  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> > new file mode 100644
> > index 000000000000..17fcbb45d121
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
> > @@ -0,0 +1,254 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> > +
> > +title: MediaTek Functional Clock Controller for MT8195
> > +
> > +maintainers:
> > +  - Chun-Jie Chen <chun-jie.chen@mediatek.com>
> > +
> > +description:
> > +  The clock architecture in Mediatek like below
> > +  PLLs -->
> > +          dividers -->
> > +                      muxes
> > +                           -->
> > +                              clock gate
> > +
> > +  The devices except apusys_pll provide clock gate control in different IP blocks.
> > +  The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - mediatek,mt8195-scp_adsp
> > +          - mediatek,mt8195-imp_iic_wrap_s
> > +          - mediatek,mt8195-imp_iic_wrap_w
> > +          - mediatek,mt8195-mfgcfg
> > +          - mediatek,mt8195-vppsys0
> > +          - mediatek,mt8195-wpesys
> > +          - mediatek,mt8195-wpesys_vpp0
> > +          - mediatek,mt8195-wpesys_vpp1
> > +          - mediatek,mt8195-vppsys1
> > +          - mediatek,mt8195-imgsys
> > +          - mediatek,mt8195-imgsys1_dip_top
> > +          - mediatek,mt8195-imgsys1_dip_nr
> > +          - mediatek,mt8195-imgsys1_wpe
> > +          - mediatek,mt8195-ipesys
> > +          - mediatek,mt8195-camsys
> > +          - mediatek,mt8195-camsys_rawa
> > +          - mediatek,mt8195-camsys_yuva
> > +          - mediatek,mt8195-camsys_rawb
> > +          - mediatek,mt8195-camsys_yuvb
> > +          - mediatek,mt8195-camsys_mraw
> > +          - mediatek,mt8195-ccusys
> > +          - mediatek,mt8195-vdecsys_soc
> > +          - mediatek,mt8195-vdecsys
> > +          - mediatek,mt8195-vdecsys_core1
> > +          - mediatek,mt8195-vencsys
> > +          - mediatek,mt8195-vencsys_core1
> > +          - mediatek,mt8195-apusys_pll
> 
> The indentation is slightly off by 2 extra spaces.

No it's not. Indentation is always 2 more that the prior keyword. If in 
doubt, make sure yamllint is installed and this is checked as part of 
the build.

Rob

  reply	other threads:[~2021-08-24 14:44 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-20 11:14 [v2 00/24] Mediatek MT8195 clock support Chun-Jie Chen
2021-08-20 11:14 ` [v2 01/24] dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock Chun-Jie Chen
2021-08-23  6:53   ` Chen-Yu Tsai
2021-08-24 14:44     ` Rob Herring [this message]
2021-08-20 11:14 ` [v2 02/24] clk: mediatek: Add dt-bindings of MT8195 clocks Chun-Jie Chen
2021-08-24 15:17   ` Rob Herring
2021-08-25 11:39   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 03/24] clk: mediatek: Fix corner case of tuner_en_reg Chun-Jie Chen
2021-08-20 11:14 ` [v2 04/24] clk: mediatek: Add API for clock resource recycle Chun-Jie Chen
2021-08-23  6:40   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 05/24] clk: mediatek: Fix resource leak in mtk_clk_simple_probe Chun-Jie Chen
2021-08-23  6:42   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 06/24] clk: mediatek: Add MT8195 apmixedsys clock support Chun-Jie Chen
2021-08-23  9:21   ` Chen-Yu Tsai
2021-08-23  9:56     ` Chen-Yu Tsai
2021-08-29 18:26   ` Stephen Boyd
2021-08-20 11:14 ` [v2 07/24] clk: mediatek: Add MT8195 topckgen " Chun-Jie Chen
2021-08-23 11:16   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 08/24] clk: mediatek: Add MT8195 peripheral " Chun-Jie Chen
2021-08-23 11:22   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 09/24] clk: mediatek: Add MT8195 infrastructure " Chun-Jie Chen
2021-08-23 11:32   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 10/24] clk: mediatek: Add MT8195 camsys " Chun-Jie Chen
2021-08-20 11:14 ` [v2 11/24] clk: mediatek: Add MT8195 ccusys " Chun-Jie Chen
2021-08-23 12:13   ` Chen-Yu Tsai
2021-09-10 10:52     ` Chun-Jie Chen
2021-08-20 11:14 ` [v2 12/24] clk: mediatek: Add MT8195 imgsys " Chun-Jie Chen
2021-08-20 11:14 ` [v2 13/24] clk: mediatek: Add MT8195 ipesys " Chun-Jie Chen
2021-08-23 12:20   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 14/24] clk: mediatek: Add MT8195 mfgcfg " Chun-Jie Chen
2021-08-23 12:02   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 15/24] clk: mediatek: Add MT8195 scp adsp " Chun-Jie Chen
2021-08-23 12:08   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 16/24] clk: mediatek: Add MT8195 vdecsys " Chun-Jie Chen
2021-08-23 12:21   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 17/24] clk: mediatek: Add MT8195 vdosys0 " Chun-Jie Chen
2021-08-25 10:52   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 18/24] clk: mediatek: Add MT8195 vdosys1 " Chun-Jie Chen
2021-08-25 10:55   ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 19/24] clk: mediatek: Add MT8195 vencsys " Chun-Jie Chen
2021-08-25 11:03   ` Chen-Yu Tsai
2021-09-10 11:09     ` Chun-Jie Chen
2021-09-14  3:47       ` Chen-Yu Tsai
2021-08-20 11:15 ` [v2 20/24] clk: mediatek: Add MT8195 vppsys0 " Chun-Jie Chen
2021-08-25 10:59   ` Chen-Yu Tsai
2021-08-20 11:15 ` [v2 21/24] clk: mediatek: Add MT8195 vppsys1 " Chun-Jie Chen
2021-08-25 11:00   ` Chen-Yu Tsai
2021-08-20 11:15 ` [v2 22/24] clk: mediatek: Add MT8195 wpesys " Chun-Jie Chen
2021-08-25 11:34   ` Chen-Yu Tsai
2021-09-10 11:04     ` Chun-Jie Chen
2021-08-20 11:15 ` [v2 23/24] clk: mediatek: Add MT8195 imp i2c wrapper " Chun-Jie Chen
2021-08-23 12:50   ` Chen-Yu Tsai
2021-08-20 11:15 ` [v2 24/24] clk: mediatek: Add MT8195 apusys " Chun-Jie Chen
2021-08-23 12:48   ` Chen-Yu Tsai

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