From: Vince Weaver <vincent.weaver@maine.edu>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Vince Weaver <vincent.weaver@maine.edu>,
Andi Kleen <ak@linux.intel.com>,
Stephane Eranian <eranian@google.com>,
"Liang, Kan" <kan.liang@intel.com>,
"mingo@redhat.com" <mingo@redhat.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"alexander.shishkin@linux.intel.com"
<alexander.shishkin@linux.intel.com>,
"acme@redhat.com" <acme@redhat.com>,
"jolsa@redhat.com" <jolsa@redhat.com>,
"torvalds@linux-foundation.org" <torvalds@linux-foundation.org>,
"tglx@linutronix.de" <tglx@linutronix.de>
Subject: Re: [PATCH 1/2] perf/x86/intel: enable CPU ref_cycles for GP counter
Date: Wed, 31 May 2017 16:57:19 -0400 (EDT) [thread overview]
Message-ID: <alpine.DEB.2.20.1705311654110.30556@macbook-air> (raw)
In-Reply-To: <20170530172555.5ya3ilfw3sowokjz@hirez.programming.kicks-ass.net>
On Tue, 30 May 2017, Peter Zijlstra wrote:
> On Wed, May 24, 2017 at 12:01:50PM -0400, Vince Weaver wrote:
> > I already have people really grumpy that you have to have one mmap() page
> > per event, meaning you sacrifice one TLB entry for each event you are
> > measuring.
>
> So there is space in that page. We could maybe look at having an array
> of stuff (max 32 entries?) which would cover a whole event group.
>
> Then you only need to mmap() the page for the leading event.
Yes, I think that was the interface they were hoping for.
I've been meaning to run some tests and see if there is a noticible hit
with TLB misses but haven't had the chance.
> Something like the below for the uapi changes I suppose. I've not
> tried to actually implement it yet, but would something like that be
> usable?
it looks usable from a quick glance. Often the problems only turn up once
you try to implement it.
Vince
>
>
> ---
> diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
> index b1c0b187acfe..40ff77e52b9d 100644
> --- a/include/uapi/linux/perf_event.h
> +++ b/include/uapi/linux/perf_event.h
> @@ -345,7 +345,8 @@ struct perf_event_attr {
> context_switch : 1, /* context switch data */
> write_backward : 1, /* Write ring buffer from end to beginning */
> namespaces : 1, /* include namespaces data */
> - __reserved_1 : 35;
> + group_pmc : 1, /* use group_pmc in perf_event_mmap_page */
> + __reserved_1 : 34;
>
> union {
> __u32 wakeup_events; /* wakeup every n events */
> @@ -469,7 +470,8 @@ struct perf_event_mmap_page {
> cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */
> cap_user_time : 1, /* The time_* fields are used */
> cap_user_time_zero : 1, /* The time_zero field is used */
> - cap_____res : 59;
> + cap_group_pmc : 1, /* The group_pmc field is used, ignore @index and @offset */
> + cap_____res : 58;
> };
> };
>
> @@ -530,11 +532,29 @@ struct perf_event_mmap_page {
> __u64 time_zero;
> __u32 size; /* Header size up to __reserved[] fields. */
>
> + __u32 __reserved_4byte_hole;
> +
> + /*
> + * If cap_group_pmc this array replaces @index and @offset. The array
> + * will contain an entry for each group member lead by the event belonging
> + * to this mmap().
> + *
> + * The @id field can be used to identify which sibling event the respective
> + * @index and @offset values belong to. Assuming an immutable group, the
> + * array index will stay constant for each event.
> + */
> + struct {
> + __u32 index;
> + __u32 __reserved_hole;
> + __s64 offset;
> + __u64 id; /* event id */
> + } group_pmc[32];
> +
> /*
> * Hole for extension of the self monitor capabilities
> */
>
> - __u8 __reserved[118*8+4]; /* align to 1k. */
> + __u8 __reserved[22*8]; /* align to 1k. */
>
> /*
> * Control data for the mmap() data buffer.
>
next prev parent reply other threads:[~2017-05-31 20:57 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-19 17:06 [PATCH 1/2] perf/x86/intel: enable CPU ref_cycles for GP counter kan.liang
2017-05-19 17:06 ` [PATCH 2/2] perf/x86/intel, watchdog: Switch NMI watchdog to ref cycles on x86 kan.liang
2017-05-22 12:03 ` Peter Zijlstra
2017-05-22 12:04 ` Peter Zijlstra
2017-05-22 16:58 ` Liang, Kan
2017-05-22 19:24 ` Peter Zijlstra
2017-05-22 18:20 ` Stephane Eranian
2017-05-22 20:01 ` Andi Kleen
2017-05-22 8:30 ` [PATCH 1/2] perf/x86/intel: enable CPU ref_cycles for GP counter Peter Zijlstra
2017-05-22 18:15 ` Stephane Eranian
2017-05-22 9:19 ` Peter Zijlstra
2017-05-22 12:22 ` Peter Zijlstra
2017-05-22 16:59 ` Liang, Kan
2017-05-22 16:55 ` Liang, Kan
2017-05-22 19:23 ` Peter Zijlstra
2017-05-22 19:28 ` Stephane Eranian
2017-05-22 21:51 ` Liang, Kan
2017-05-23 6:39 ` Peter Zijlstra
2017-05-23 6:42 ` Stephane Eranian
2017-05-24 15:45 ` Andi Kleen
2017-05-24 16:01 ` Vince Weaver
2017-05-24 16:55 ` Andi Kleen
2017-05-28 20:31 ` Stephane Eranian
2017-05-30 9:25 ` Peter Zijlstra
2017-05-30 13:51 ` Andi Kleen
2017-05-30 16:28 ` Peter Zijlstra
2017-05-30 16:41 ` Stephane Eranian
2017-05-30 17:22 ` Andi Kleen
2017-05-30 17:40 ` Peter Zijlstra
2017-05-30 17:51 ` Andi Kleen
2017-05-30 18:59 ` Peter Zijlstra
2017-05-30 19:40 ` Andi Kleen
2017-05-30 16:39 ` Stephane Eranian
2017-05-30 16:55 ` Thomas Gleixner
2017-05-30 17:25 ` Peter Zijlstra
2017-05-31 20:57 ` Vince Weaver [this message]
2017-05-28 2:56 ` kbuild test robot
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