[PATCH 00/14] Drop PCIE_AUX_CLK from the PCIe PHY nodes of Qcom SoCs

[PATCH 00/14] Drop PCIE_AUX_CLK from the PCIe PHY nodes of Qcom SoCs

[Manivannan Sadhasivam]

Hello,

This series fixes a longstanding but recently identified issue on Qcom
platforms regarding the use of PCIE_AUX_CLK in PCIe PHY nodes. While trying
to remove the PCIE_GDSC power domain from the PCIe PHY nodes, Johan reported
[1] that he encountered "gcc_pcie_3b_aux_clk status stuck at 'off'" issue on
the X13s while powering up the PCIe PHY without enabling the PCIE_GDSC.

This confirmed that the "gcc_pcie_3b_aux_clk" depends on PCIE_GDSC. But the
name of the clock implies that it is used by the PCIe controller. So I checked
with Qcom internally and confirmed that this clock belongs to the controller,
not PHY.

But on some SoCs, there is a separate PCIE_PHY_AUX_CLK for the PHY to keep the
link stable during the PCIe L1SS state. But due to some reasons, that clock is
powered by PCIE_GDSC.

So to conclude, PCIE_AUX_CLK belongs to the controller and it depends on
PCIE_GDSC, so it should be removed from the PHY nodes. On the other hand,
PCIE_PHY_AUX_CLK belongs to the PHY and it also depends on the PCIE_GDSC. So for
the PHY instances that require this clock, PCIE_GDSC should be added as a
second power domain along with MX domain which is applicable to all PHYs.

This series removes the PCIE_AUX_CLK from PCIe PHY nodes of all SoCs and also
makes the changes to the bindings to reflect the same. I will also submit a
followup series to fix the PHY power domain across all SoCs.

NOTE: I haven't added the Fixes tag on purpose, since the patches are getting
backported by the stable team whenever the tag is present and if both the
binding and dts patches didn't get backported to a release, then it will cause
ABI break.

- Mani

[1] https://lore.kernel.org/lkml/ZY6sh8nlEUyEfL0u@hovoldconsulting.com/

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Manivannan Sadhasivam (14):
      dt-bindings: phy: qcom,ipq8074-qmp-pcie: Drop PCIE_AUX_CLK from pcie_phy node
      arm64: dts: qcom: ipq6018: Drop PCIE_AUX_CLK from pcie_phy node
      arm64: dts: qcom: ipq8074: Drop PCIE_AUX_CLK from pcie_phy nodes
      dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Fix the usage of aux clk
      dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document missing compatible for SM8350 3x2 PHY
      phy: qcom: qmp-pcie: Add a new compatible for SC7280 SoC
      phy: qcom: qmp-pcie: Add a comment to clarify the use of "aux and "phy_aux" clocks
      arm64: dts: qcom: sc7280: Drop PCIE_AUX_CLK from pcie_phy node
      arm64: dts: qcom: sc8280xp: Drop PCIE_AUX_CLK from pcie_phy nodes
      arm64: dts: qcom: sm8350: Drop PCIE_AUX_CLK from pcie_phy nodes
      arm64: dts: qcom: sm8450: Drop PCIE_AUX_CLK from pcie_phy node
      arm64: dts: qcom: sm8550: Drop PCIE_AUX_CLK from pcie_phy node
      arm64: dts: qcom: sm8650: Drop PCIE_AUX_CLK from pcie_phy node
      arm64: dts: qcom: sa8775p: Drop PCIE_AUX_CLK from pcie_phy nodes

 .../bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml    |  9 +--
 .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml   | 81 ++++++++++++++--------
 arch/arm64/boot/dts/qcom/ipq6018.dtsi              |  6 +-
 arch/arm64/boot/dts/qcom/ipq8074.dtsi              | 12 ++--
 arch/arm64/boot/dts/qcom/sa8775p.dtsi              | 14 ++--
 arch/arm64/boot/dts/qcom/sc7280.dtsi               |  8 +--
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi             | 25 +++----
 arch/arm64/boot/dts/qcom/sm8350.dtsi               | 10 ++-
 arch/arm64/boot/dts/qcom/sm8450.dtsi               |  6 +-
 arch/arm64/boot/dts/qcom/sm8550.dtsi               |  6 +-
 arch/arm64/boot/dts/qcom/sm8650.dtsi               |  6 +-
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c           | 13 +++-
 12 files changed, 104 insertions(+), 92 deletions(-)
---
base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d
change-id: 20240122-pcie-aux-clk-fix-094bc77a16ba

Best regards,
-- 
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

[PATCH 01/14] dt-bindings: phy: qcom,ipq8074-qmp-pcie: Drop PCIE_AUX_CLK from pcie_phy node

[Manivannan Sadhasivam]

PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
only required by the PCIe controller. Hence drop it from the binding.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 .../devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml       | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
index 634cec5d57ea..a953ac197dfd 100644
--- a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
@@ -25,11 +25,10 @@ properties:
       - description: serdes
 
   clocks:
-    maxItems: 3
+    maxItems: 2
 
   clock-names:
     items:
-      - const: aux
       - const: cfg_ahb
       - const: pipe
 
@@ -72,11 +71,9 @@ examples:
         compatible = "qcom,ipq6018-qmp-pcie-phy";
         reg = <0x00084000 0x1000>;
 
-        clocks = <&gcc GCC_PCIE0_AUX_CLK>,
-                 <&gcc GCC_PCIE0_AHB_CLK>,
+        clocks = <&gcc GCC_PCIE0_AHB_CLK>,
                  <&gcc GCC_PCIE0_PIPE_CLK>;
-        clock-names = "aux",
-                      "cfg_ahb",
+        clock-names = "cfg_ahb",
                       "pipe";
 
         clock-output-names = "gcc_pcie0_pipe_clk_src";

-- 
2.25.1

[PATCH 02/14] arm64: dts: qcom: ipq6018: Drop PCIE_AUX_CLK from pcie_phy node

[Manivannan Sadhasivam]

PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
only required by the PCIe controller. Hence drop it from pcie_phy node.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 5e1277fea725..1767e5abd76d 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -283,11 +283,9 @@ pcie_phy: phy@84000 {
 			reg = <0x0 0x00084000 0x0 0x1000>;
 			status = "disabled";
 
-			clocks = <&gcc GCC_PCIE0_AUX_CLK>,
-				<&gcc GCC_PCIE0_AHB_CLK>,
+			clocks = <&gcc GCC_PCIE0_AHB_CLK>,
 				<&gcc GCC_PCIE0_PIPE_CLK>;
-			clock-names = "aux",
-				      "cfg_ahb",
+			clock-names = "cfg_ahb",
 				      "pipe";
 
 			clock-output-names = "gcc_pcie0_pipe_clk_src";

-- 
2.25.1

[PATCH 03/14] arm64: dts: qcom: ipq8074: Drop PCIE_AUX_CLK from pcie_phy nodes

[Manivannan Sadhasivam]

PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
only required by the PCIe controller. Hence drop it from pcie_phy nodes.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index cf295bed3299..6ae6833e8969 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -201,11 +201,9 @@ pcie_qmp0: phy@84000 {
 			compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
 			reg = <0x00084000 0x1000>;
 
-			clocks = <&gcc GCC_PCIE0_AUX_CLK>,
-				 <&gcc GCC_PCIE0_AHB_CLK>,
+			clocks = <&gcc GCC_PCIE0_AHB_CLK>,
 				 <&gcc GCC_PCIE0_PIPE_CLK>;
-			clock-names = "aux",
-				      "cfg_ahb",
+			clock-names = "cfg_ahb",
 				      "pipe";
 
 			clock-output-names = "pcie20_phy0_pipe_clk";
@@ -224,11 +222,9 @@ pcie_qmp1: phy@8e000 {
 			compatible = "qcom,ipq8074-qmp-pcie-phy";
 			reg = <0x0008e000 0x1000>;
 
-			clocks = <&gcc GCC_PCIE1_AUX_CLK>,
-				 <&gcc GCC_PCIE1_AHB_CLK>,
+			clocks = <&gcc GCC_PCIE1_AHB_CLK>,
 				 <&gcc GCC_PCIE1_PIPE_CLK>;
-			clock-names = "aux",
-				      "cfg_ahb",
+			clock-names = "cfg_ahb",
 				      "pipe";
 
 			clock-output-names = "pcie20_phy1_pipe_clk";

-- 
2.25.1

[PATCH 04/14] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Fix the usage of aux clk

[Manivannan Sadhasivam]

On some platforms, PHY block requires PCIE_PHY_AUX_CLK to be used when the
PCIe link enters L1SS state. On those platforms, a dedicated
PCIE_PHY_AUX_CLK is available from GCC. Other than this, the PHY block
doesn't require any other "aux" clock, including PCIE_AUX_CLK which only
required by the PCIe controller.

Historically, the DTs of the platforms requiring "aux" clock passed
PCIE_PHY_AUX_CLK as "aux" clock. But over the period of time, platforms
that do not require this dedicated "aux" clock mistakenly started passing
the PCIE_AUX_CLK as the "aux" clock. More recently, SA8775P platform passed
both "aux" (PCIE_AUX_CLK) and "phy_aux" (PCIE_PHY_AUX_CLK) clocks.

So to clean up this mess, let's remove the newly introduced "phy_aux" clock
and just use "aux" clock to supply PCIE_PHY_AUX_CLK for platforms that
require it. For the platforms that do not require a dedicated "aux" clock,
the clock is removed from DT.

While at it, let's also define "qcom,sc7280-qmp-pcie-phy" compatible for
SC7280 SoC which was earlier using the compatible
"qcom,sm8250-qmp-gen3x2-pcie-phy" as the clock requirement has changed and
also restructure the "clock-names" property for the affected platforms.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml   | 79 ++++++++++++++--------
 1 file changed, 52 insertions(+), 27 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
index 6c03f2d5fca3..2396a457f9c8 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
@@ -18,6 +18,7 @@ properties:
     enum:
       - qcom,sa8775p-qmp-gen4x2-pcie-phy
       - qcom,sa8775p-qmp-gen4x4-pcie-phy
+      - qcom,sc7280-qmp-pcie-phy
       - qcom,sc8180x-qmp-pcie-phy
       - qcom,sc8280xp-qmp-gen3x1-pcie-phy
       - qcom,sc8280xp-qmp-gen3x2-pcie-phy
@@ -44,19 +45,12 @@ properties:
     maxItems: 2
 
   clocks:
-    minItems: 5
-    maxItems: 7
+    minItems: 4
+    maxItems: 6
 
   clock-names:
-    minItems: 5
-    items:
-      - const: aux
-      - const: cfg_ahb
-      - const: ref
-      - enum: [rchng, refgen]
-      - const: pipe
-      - const: pipediv2
-      - const: phy_aux
+    minItems: 4
+    maxItems: 6
 
   power-domains:
     maxItems: 1
@@ -130,6 +124,28 @@ allOf:
         reg:
           maxItems: 1
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sc7280-qmp-pcie-phy
+              - qcom,sm8350-qmp-gen3x1-pcie-phy
+              - qcom,sm8450-qmp-gen3x1-pcie-phy
+              - qcom,sm8450-qmp-gen3x2-pcie-phy
+              - qcom,sm8550-qmp-gen3x2-pcie-phy
+              - qcom,sm8650-qmp-gen3x2-pcie-phy
+    then:
+      properties:
+        clocks:
+          maxItems: 4
+        clock-names:
+          items:
+            - const: cfg_ahb
+            - const: ref
+            - enum: [rchng, refgen]
+            - const: pipe
+
   - if:
       properties:
         compatible:
@@ -144,19 +160,19 @@ allOf:
               - qcom,sm8250-qmp-gen3x1-pcie-phy
               - qcom,sm8250-qmp-gen3x2-pcie-phy
               - qcom,sm8250-qmp-modem-pcie-phy
-              - qcom,sm8350-qmp-gen3x1-pcie-phy
-              - qcom,sm8450-qmp-gen3x1-pcie-phy
-              - qcom,sm8450-qmp-gen3x2-pcie-phy
-              - qcom,sm8550-qmp-gen3x2-pcie-phy
               - qcom,sm8550-qmp-gen4x2-pcie-phy
-              - qcom,sm8650-qmp-gen3x2-pcie-phy
               - qcom,sm8650-qmp-gen4x2-pcie-phy
     then:
       properties:
         clocks:
           maxItems: 5
         clock-names:
-          maxItems: 5
+          items:
+            - const: aux
+            - const: cfg_ahb
+            - const: ref
+            - enum: [rchng, refgen]
+            - const: pipe
 
   - if:
       properties:
@@ -169,9 +185,14 @@ allOf:
     then:
       properties:
         clocks:
-          minItems: 6
+          maxItems: 5
         clock-names:
-          minItems: 6
+          items:
+            - const: cfg_ahb
+            - const: ref
+            - const: rchng
+            - const: pipe
+            - const: pipediv2
 
   - if:
       properties:
@@ -183,9 +204,15 @@ allOf:
     then:
       properties:
         clocks:
-          minItems: 7
+          minItems: 6
         clock-names:
-          minItems: 7
+          items:
+            - const: aux
+            - const: cfg_ahb
+            - const: ref
+            - const: rchng
+            - const: pipe
+            - const: pipediv2
 
   - if:
       properties:
@@ -215,13 +242,12 @@ examples:
       compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
       reg = <0x01c18000 0x2000>;
 
-      clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
-               <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
+      clocks = <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
                <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
                <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
                <&gcc GCC_PCIE_2B_PIPE_CLK>,
                <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
-      clock-names = "aux", "cfg_ahb", "ref", "rchng",
+      clock-names = "cfg_ahb", "ref", "rchng",
                     "pipe", "pipediv2";
 
       power-domains = <&gcc PCIE_2B_GDSC>;
@@ -242,13 +268,12 @@ examples:
       compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
       reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
 
-      clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
-               <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
+      clocks = <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
                <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
                <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
                <&gcc GCC_PCIE_2A_PIPE_CLK>,
                <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
-      clock-names = "aux", "cfg_ahb", "ref", "rchng",
+      clock-names = "cfg_ahb", "ref", "rchng",
                     "pipe", "pipediv2";
 
       power-domains = <&gcc PCIE_2A_GDSC>;

-- 
2.25.1

[PATCH 05/14] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document missing compatible for SM8350 3x2 PHY

[Manivannan Sadhasivam]

Document the compatible for SM8350 PCIe Gen3 x2 lane PHY.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
index 2396a457f9c8..77338184cdb4 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
@@ -33,6 +33,7 @@ properties:
       - qcom,sm8250-qmp-gen3x2-pcie-phy
       - qcom,sm8250-qmp-modem-pcie-phy
       - qcom,sm8350-qmp-gen3x1-pcie-phy
+      - qcom,sm8350-qmp-gen3x2-pcie-phy
       - qcom,sm8450-qmp-gen3x1-pcie-phy
       - qcom,sm8450-qmp-gen4x2-pcie-phy
       - qcom,sm8550-qmp-gen3x2-pcie-phy
@@ -131,6 +132,7 @@ allOf:
             enum:
               - qcom,sc7280-qmp-pcie-phy
               - qcom,sm8350-qmp-gen3x1-pcie-phy
+              - qcom,sm8350-qmp-gen3x2-pcie-phy
               - qcom,sm8450-qmp-gen3x1-pcie-phy
               - qcom,sm8450-qmp-gen3x2-pcie-phy
               - qcom,sm8550-qmp-gen3x2-pcie-phy

-- 
2.25.1

[PATCH 06/14] phy: qcom: qmp-pcie: Add a new compatible for SC7280 SoC

[Manivannan Sadhasivam]

Since this platform requires different clocks compared to SM8250, use a
different compatible. But the drvdata of SM8250 can be reused safely.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 2af7115ef968..9a220cbd9615 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -3822,6 +3822,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
 	}, {
 		.compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy",
 		.data = &sa8775p_qmp_gen4x4_pciephy_cfg,
+	}, {
+		.compatible = "qcom,sc7280-qmp-pcie-phy",
+		.data = &sm8250_qmp_gen3x2_pciephy_cfg,
 	}, {
 		.compatible = "qcom,sc8180x-qmp-pcie-phy",
 		.data = &sc8180x_pciephy_cfg,

-- 
2.25.1

[PATCH 07/14] phy: qcom: qmp-pcie: Add a comment to clarify the use of "aux and "phy_aux" clocks

[Manivannan Sadhasivam]

PCIe PHY hw on some SoCs require PCIE_PHY_AUX_CLK when the link enters L1SS
state. Historically, DTs of those SoCs passed this clock as "aux" clock.
But, SA8775P passed PCIE_PHY_AUX_CLK as "phy_aux" and PCIE_AUX_CLK as "aux"
mistakenly as the latter is not needed at all. Even though the SA8775P DT
got fixed, both of these clocks are kept here for backwards compatibility.

So add a comment to make it clear.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 9a220cbd9615..044e3c5ba341 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -2328,7 +2328,15 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
 	readl(base + offset);
 }
 
-/* list of clocks required by phy */
+/* list of clocks required by phy
+ *
+ * PCIe PHY hw on some SoCs require PCIE_PHY_AUX_CLK when the link enters L1SS
+ * state. Historically, DTs of those SoCs passed this clock as "aux" clock. But,
+ * SA8775P passed PCIE_PHY_AUX_CLK as "phy_aux" and PCIE_AUX_CLK as "aux"
+ * mistakenly as the latter is not needed at all. Even though the SA8775P DT got
+ * fixed, both of these clocks are kept here for backwards compatibility.
+ */
+
 static const char * const qmp_pciephy_clk_l[] = {
 	"aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux",
 };

-- 
2.25.1

[PATCH 08/14] arm64: dts: qcom: sc7280: Drop PCIE_AUX_CLK from pcie_phy node

[Manivannan Sadhasivam]

PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
only required by the PCIe controller. Hence drop it from pcie_phy node.

This also warrants a new compatible as the clocks differ between SC7280 and
SM8250.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 83b5b76ba179..00fa14777417 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2238,15 +2238,13 @@ pcie1: pcie@1c08000 {
 		};
 
 		pcie1_phy: phy@1c0e000 {
-			compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
+			compatible = "qcom,sc7280-qmp-pcie-phy";
 			reg = <0 0x01c0e000 0 0x1000>;
-			clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
-				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+			clocks = <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
 				 <&gcc GCC_PCIE_CLKREF_EN>,
 				 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
 				 <&gcc GCC_PCIE_1_PIPE_CLK>;
-			clock-names = "aux",
-				      "cfg_ahb",
+			clock-names = "cfg_ahb",
 				      "ref",
 				      "refgen",
 				      "pipe";

-- 
2.25.1

[PATCH 09/14] arm64: dts: qcom: sc8280xp: Drop PCIE_AUX_CLK from pcie_phy nodes

[Manivannan Sadhasivam]

PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
only required by the PCIe controller. Hence drop it from pcie_phy nodes.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 ++++++++++---------------
 1 file changed, 10 insertions(+), 15 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index febf28356ff8..cc33ef47d5a7 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1785,13 +1785,12 @@ pcie4_phy: phy@1c06000 {
 			compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
 			reg = <0x0 0x01c06000 0x0 0x2000>;
 
-			clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
-				 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
+			clocks = <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
 				 <&gcc GCC_PCIE_4_CLKREF_CLK>,
 				 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
 				 <&gcc GCC_PCIE_4_PIPE_CLK>,
 				 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
-			clock-names = "aux", "cfg_ahb", "ref", "rchng",
+			clock-names = "cfg_ahb", "ref", "rchng",
 				      "pipe", "pipediv2";
 
 			assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
@@ -1883,13 +1882,12 @@ pcie3b_phy: phy@1c0e000 {
 			compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
 			reg = <0x0 0x01c0e000 0x0 0x2000>;
 
-			clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
-				 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
+			clocks = <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
 				 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
 				 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
 				 <&gcc GCC_PCIE_3B_PIPE_CLK>,
 				 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
-			clock-names = "aux", "cfg_ahb", "ref", "rchng",
+			clock-names = "cfg_ahb", "ref", "rchng",
 				      "pipe", "pipediv2";
 
 			assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
@@ -1982,13 +1980,12 @@ pcie3a_phy: phy@1c14000 {
 			reg = <0x0 0x01c14000 0x0 0x2000>,
 			      <0x0 0x01c16000 0x0 0x2000>;
 
-			clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
-				 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
+			clocks = <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
 				 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
 				 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
 				 <&gcc GCC_PCIE_3A_PIPE_CLK>,
 				 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
-			clock-names = "aux", "cfg_ahb", "ref", "rchng",
+			clock-names = "cfg_ahb", "ref", "rchng",
 				      "pipe", "pipediv2";
 
 			assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
@@ -2082,13 +2079,12 @@ pcie2b_phy: phy@1c1e000 {
 			compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
 			reg = <0x0 0x01c1e000 0x0 0x2000>;
 
-			clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
-				 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
+			clocks = <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
 				 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
 				 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
 				 <&gcc GCC_PCIE_2B_PIPE_CLK>,
 				 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
-			clock-names = "aux", "cfg_ahb", "ref", "rchng",
+			clock-names = "cfg_ahb", "ref", "rchng",
 				      "pipe", "pipediv2";
 
 			assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
@@ -2181,13 +2177,12 @@ pcie2a_phy: phy@1c24000 {
 			reg = <0x0 0x01c24000 0x0 0x2000>,
 			      <0x0 0x01c26000 0x0 0x2000>;
 
-			clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
-				 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
+			clocks = <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
 				 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
 				 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
 				 <&gcc GCC_PCIE_2A_PIPE_CLK>,
 				 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
-			clock-names = "aux", "cfg_ahb", "ref", "rchng",
+			clock-names = "cfg_ahb", "ref", "rchng",
 				      "pipe", "pipediv2";
 
 			assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;

-- 
2.25.1

[PATCH 10/14] arm64: dts: qcom: sm8350: Drop PCIE_AUX_CLK from pcie_phy nodes

[Manivannan Sadhasivam]

PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
only required by the PCIe controller. Hence drop it from pcie_phy nodes.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index e78c83a897c2..23a9060f21d9 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1571,12 +1571,11 @@ pcie0: pcie@1c00000 {
 		pcie0_phy: phy@1c06000 {
 			compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
 			reg = <0 0x01c06000 0 0x2000>;
-			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
-				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+			clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 				 <&gcc GCC_PCIE_0_CLKREF_EN>,
 				 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
 				 <&gcc GCC_PCIE_0_PIPE_CLK>;
-			clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
+			clock-names = "cfg_ahb", "ref", "rchng", "pipe";
 
 			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
 			reset-names = "phy";
@@ -1654,12 +1653,11 @@ pcie1: pcie@1c08000 {
 		pcie1_phy: phy@1c0e000 {
 			compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
 			reg = <0 0x01c0e000 0 0x2000>;
-			clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
-				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+			clocks = <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
 				 <&gcc GCC_PCIE_1_CLKREF_EN>,
 				 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
 				 <&gcc GCC_PCIE_1_PIPE_CLK>;
-			clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
+			clock-names = "cfg_ahb", "ref", "rchng", "pipe";
 
 			resets = <&gcc GCC_PCIE_1_PHY_BCR>;
 			reset-names = "phy";

-- 
2.25.1

[PATCH 11/14] arm64: dts: qcom: sm8450: Drop PCIE_AUX_CLK from pcie_phy node

[Manivannan Sadhasivam]

PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
only required by the PCIe controller. Hence drop it from pcie_phy node.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 01e4dfc4babd..1e0091dabaf1 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -1830,13 +1830,11 @@ pcie0_phy: phy@1c06000 {
 			compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
 			reg = <0 0x01c06000 0 0x2000>;
 
-			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
-				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+			clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 				 <&gcc GCC_PCIE_0_CLKREF_EN>,
 				 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
 				 <&gcc GCC_PCIE_0_PIPE_CLK>;
-			clock-names = "aux",
-				      "cfg_ahb",
+			clock-names = "cfg_ahb",
 				      "ref",
 				      "rchng",
 				      "pipe";

-- 
2.25.1

[PATCH 12/14] arm64: dts: qcom: sm8550: Drop PCIE_AUX_CLK from pcie_phy node

[Manivannan Sadhasivam]

PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
only required by the PCIe controller. Hence drop it from pcie_phy node.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index ee1ba5a8c8fc..f074683f7940 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1760,13 +1760,11 @@ pcie0_phy: phy@1c06000 {
 			compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
 			reg = <0 0x01c06000 0 0x2000>;
 
-			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
-				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+			clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 				 <&tcsr TCSR_PCIE_0_CLKREF_EN>,
 				 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
 				 <&gcc GCC_PCIE_0_PIPE_CLK>;
-			clock-names = "aux", "cfg_ahb", "ref", "rchng",
-				      "pipe";
+			clock-names = "cfg_ahb", "ref", "rchng", "pipe";
 
 			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
 			reset-names = "phy";

-- 
2.25.1

[PATCH 13/14] arm64: dts: qcom: sm8650: Drop PCIE_AUX_CLK from pcie_phy node

[Manivannan Sadhasivam]

PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
only required by the PCIe controller. Hence drop it from pcie_phy node.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 2df77123a8c7..b31e60599891 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2276,13 +2276,11 @@ pcie0_phy: phy@1c06000 {
 			compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy";
 			reg = <0 0x01c06000 0 0x2000>;
 
-			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
-				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+			clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 				 <&tcsr TCSR_PCIE_0_CLKREF_EN>,
 				 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
 				 <&gcc GCC_PCIE_0_PIPE_CLK>;
-			clock-names = "aux",
-				      "cfg_ahb",
+			clock-names = "cfg_ahb",
 				      "ref",
 				      "rchng",
 				      "pipe";

-- 
2.25.1

[PATCH 14/14] arm64: dts: qcom: sa8775p: Drop PCIE_AUX_CLK from pcie_phy nodes

[Manivannan Sadhasivam]

PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
only required by the PCIe controller. Hence drop it from pcie_phy nodes.

While at it, let's also rename "phy_aux" clock to "aux" clock and move it
to first entry to maintain uniformity with other SoCs.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index a7eaca33d326..b99626c52800 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3590,16 +3590,15 @@ pcie0_phy: phy@1c04000 {
 		compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
 		reg = <0x0 0x1c04000 0x0 0x2000>;
 
-		clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+		clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
 			 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 			 <&gcc GCC_PCIE_CLKREF_EN>,
 			 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
 			 <&gcc GCC_PCIE_0_PIPE_CLK>,
-			 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
-			 <&gcc GCC_PCIE_0_PHY_AUX_CLK>;
+			 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>;
 
 		clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
-			      "pipediv2", "phy_aux";
+			      "pipediv2";
 
 		assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
 		assigned-clock-rates = <100000000>;
@@ -3690,16 +3689,15 @@ pcie1_phy: phy@1c14000 {
 		compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
 		reg = <0x0 0x1c14000 0x0 0x4000>;
 
-		clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+		clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
 			 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
 			 <&gcc GCC_PCIE_CLKREF_EN>,
 			 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
 			 <&gcc GCC_PCIE_1_PIPE_CLK>,
-			 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
-			 <&gcc GCC_PCIE_1_PHY_AUX_CLK>;
+			 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
 
 		clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
-			      "pipediv2", "phy_aux";
+			      "pipediv2";
 
 		assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
 		assigned-clock-rates = <100000000>;

-- 
2.25.1

Re: [PATCH 12/14] arm64: dts: qcom: sm8550: Drop PCIE_AUX_CLK from pcie_phy node

[neil.armstrong]

On 24/01/2024 08:36, Manivannan Sadhasivam wrote:
> PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
> only required by the PCIe controller. Hence drop it from pcie_phy node.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>   arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++----
>   1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index ee1ba5a8c8fc..f074683f7940 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1760,13 +1760,11 @@ pcie0_phy: phy@1c06000 {
>   			compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
>   			reg = <0 0x01c06000 0 0x2000>;
>   
> -			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> -				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +			clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>   				 <&tcsr TCSR_PCIE_0_CLKREF_EN>,
>   				 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
>   				 <&gcc GCC_PCIE_0_PIPE_CLK>;
> -			clock-names = "aux", "cfg_ahb", "ref", "rchng",
> -				      "pipe";
> +			clock-names = "cfg_ahb", "ref", "rchng", "pipe";
>   
>   			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
>   			reset-names = "phy";
> 


Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK

Re: [PATCH 13/14] arm64: dts: qcom: sm8650: Drop PCIE_AUX_CLK from pcie_phy node

[neil.armstrong]

On 24/01/2024 08:36, Manivannan Sadhasivam wrote:
> PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
> only required by the PCIe controller. Hence drop it from pcie_phy node.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>   arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 ++----
>   1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index 2df77123a8c7..b31e60599891 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -2276,13 +2276,11 @@ pcie0_phy: phy@1c06000 {
>   			compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy";
>   			reg = <0 0x01c06000 0 0x2000>;
>   
> -			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> -				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +			clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>   				 <&tcsr TCSR_PCIE_0_CLKREF_EN>,
>   				 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
>   				 <&gcc GCC_PCIE_0_PIPE_CLK>;
> -			clock-names = "aux",
> -				      "cfg_ahb",
> +			clock-names = "cfg_ahb",
>   				      "ref",
>   				      "rchng",
>   				      "pipe";
> 

Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD

Re: [PATCH 09/14] arm64: dts: qcom: sc8280xp: Drop PCIE_AUX_CLK from pcie_phy nodes

[Konrad Dybcio]

On 1/24/24 08:36, Manivannan Sadhasivam wrote:
> PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
> only required by the PCIe controller. Hence drop it from pcie_phy nodes.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---

So, I have a small phytest module that basically does this:

phy_get
phy_init
phy_set_mode_ext(PCIE_RC)
phy_power_on

To load it, I skip PCIe init (comment out the node), then wait for clk
and pmdomain unused cleanup, then load the phytest module to ensure that
I'm not piggybacking off of the RC's resources.

I tried it out on the CRD, on PCIE2A (NVMe)

Without this patch, the PHY seems to init fine

With this patch, I get:

(1) qcom-qmp-pcie-phy 1c24000.phy: phy initialization timed-out


Kicking the PCIe GDSC from the PHY, I additionally get:

(2) gcc_pcie_2a_cfg_ahb_clk status stuck at 'off'


I think we expected (2), but is (1) okay?

Konrad

Re: [PATCH 04/14] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Fix the usage of aux clk

[Krzysztof Kozlowski]

On 24/01/2024 08:36, Manivannan Sadhasivam wrote:
> On some platforms, PHY block requires PCIE_PHY_AUX_CLK to be used when the
> PCIe link enters L1SS state. On those platforms, a dedicated
> PCIE_PHY_AUX_CLK is available from GCC. Other than this, the PHY block
> doesn't require any other "aux" clock, including PCIE_AUX_CLK which only
> required by the PCIe controller.
> 
> Historically, the DTs of the platforms requiring "aux" clock passed
> PCIE_PHY_AUX_CLK as "aux" clock. But over the period of time, platforms
> that do not require this dedicated "aux" clock mistakenly started passing
> the PCIE_AUX_CLK as the "aux" clock. More recently, SA8775P platform passed
> both "aux" (PCIE_AUX_CLK) and "phy_aux" (PCIE_PHY_AUX_CLK) clocks.
> 
> So to clean up this mess, let's remove the newly introduced "phy_aux" clock
> and just use "aux" clock to supply PCIE_PHY_AUX_CLK for platforms that
> require it. For the platforms that do not require a dedicated "aux" clock,
> the clock is removed from DT.
> 
> While at it, let's also define "qcom,sc7280-qmp-pcie-phy" compatible for
> SC7280 SoC which was earlier using the compatible
> "qcom,sm8250-qmp-gen3x2-pcie-phy" as the clock requirement has changed and
> also restructure the "clock-names" property for the affected platforms.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 05/14] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document missing compatible for SM8350 3x2 PHY

[Krzysztof Kozlowski]

On 24/01/2024 08:36, Manivannan Sadhasivam wrote:
> Document the compatible for SM8350 PCIe Gen3 x2 lane PHY.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>  Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 01/14] dt-bindings: phy: qcom,ipq8074-qmp-pcie: Drop PCIE_AUX_CLK from pcie_phy node

[Krzysztof Kozlowski]

On 24/01/2024 08:36, Manivannan Sadhasivam wrote:
> PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
> only required by the PCIe controller. Hence drop it from the binding.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>  .../devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml       | 9 +++------
>  1 file changed, 3 insertions(+), 6 deletions(-)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 04/14] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Fix the usage of aux clk

[Vinod Koul]

On 24-01-24, 13:06, Manivannan Sadhasivam wrote:
> On some platforms, PHY block requires PCIE_PHY_AUX_CLK to be used when the
> PCIe link enters L1SS state. On those platforms, a dedicated
> PCIE_PHY_AUX_CLK is available from GCC. Other than this, the PHY block
> doesn't require any other "aux" clock, including PCIE_AUX_CLK which only
> required by the PCIe controller.
> 
> Historically, the DTs of the platforms requiring "aux" clock passed
> PCIE_PHY_AUX_CLK as "aux" clock. But over the period of time, platforms
> that do not require this dedicated "aux" clock mistakenly started passing
> the PCIE_AUX_CLK as the "aux" clock. More recently, SA8775P platform passed
> both "aux" (PCIE_AUX_CLK) and "phy_aux" (PCIE_PHY_AUX_CLK) clocks.
> 
> So to clean up this mess, let's remove the newly introduced "phy_aux" clock
> and just use "aux" clock to supply PCIE_PHY_AUX_CLK for platforms that
> require it. For the platforms that do not require a dedicated "aux" clock,
> the clock is removed from DT.
> 
> While at it, let's also define "qcom,sc7280-qmp-pcie-phy" compatible for
> SC7280 SoC which was earlier using the compatible
> "qcom,sm8250-qmp-gen3x2-pcie-phy" as the clock requirement has changed and
> also restructure the "clock-names" property for the affected platforms.

This one fails to apply for me

-- 
~Vinod