From: Reinette Chatre <reinette.chatre@intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: tglx@linutronix.de, mingo@redhat.com, fenghua.yu@intel.com,
tony.luck@intel.com, vikas.shivappa@linux.intel.com,
gavin.hindman@intel.com, jithu.joseph@intel.com,
dave.hansen@intel.com, hpa@zytor.com, x86@kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/2] x86/intel_rdt and perf/x86: Fix lack of coordination with perf
Date: Thu, 2 Aug 2018 09:44:13 -0700 [thread overview]
Message-ID: <f990df31-ab75-974e-b142-47af07a33a08@intel.com> (raw)
In-Reply-To: <20180802161823.GJ2458@hirez.programming.kicks-ass.net>
On 8/2/2018 9:18 AM, Peter Zijlstra wrote:
> On Thu, Aug 02, 2018 at 09:14:10AM -0700, Reinette Chatre wrote:
>
>> The current implementation does not coordinate with perf and this is
>> what I am trying to fix in this series.
>>
>> I do respect your NAK but it is not clear to me how to proceed after
>> obtaining it. Could you please elaborate on what you would prefer as a
>> solution to ensure accurate measurement of cache-locked data that is
>> better integrated?
>
> We have an in-kernel interface to perf, use that if you want access to
> the PMU. You will not directly stomp on PMU registers.
I do not see how I can do so without incurring the cache hits and misses
from the data needed and instructions run by this interface. Could you
please share how I can do so and still obtain the accurate measurement
of cache residency of a specific memory region?
Reinette
next prev parent reply other threads:[~2018-08-02 16:44 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-31 19:38 [PATCH 0/2] x86/intel_rdt and perf/x86: Fix lack of coordination with perf Reinette Chatre
2018-07-31 19:38 ` [PATCH 1/2] perf/x86: Expose PMC hardware reservation Reinette Chatre
2018-07-31 19:38 ` [PATCH 2/2] x86/intel_rdt: Coordinate performance monitoring with perf Reinette Chatre
2018-08-02 12:39 ` [PATCH 0/2] x86/intel_rdt and perf/x86: Fix lack of coordination " Peter Zijlstra
2018-08-02 16:14 ` Reinette Chatre
2018-08-02 16:18 ` Peter Zijlstra
2018-08-02 16:44 ` Reinette Chatre [this message]
2018-08-02 17:37 ` Peter Zijlstra
2018-08-02 18:18 ` Dave Hansen
2018-08-02 19:54 ` Peter Zijlstra
2018-08-02 20:06 ` Dave Hansen
2018-08-02 20:13 ` Peter Zijlstra
2018-08-02 20:43 ` Reinette Chatre
2018-08-03 10:49 ` Peter Zijlstra
2018-08-03 15:18 ` Reinette Chatre
2018-08-03 15:25 ` Peter Zijlstra
2018-08-03 18:37 ` Reinette Chatre
2018-08-06 19:50 ` Reinette Chatre
2018-08-06 22:12 ` Peter Zijlstra
2018-08-06 23:07 ` Reinette Chatre
2018-08-07 9:36 ` Peter Zijlstra
[not found] ` <ace0bebb-91ab-5d40-e7d7-d72d48302fa8@intel.com>
2018-08-08 1:28 ` Luck, Tony
2018-08-08 5:44 ` Reinette Chatre
2018-08-08 7:41 ` Peter Zijlstra
2018-08-08 15:55 ` Luck, Tony
2018-08-08 16:47 ` Peter Zijlstra
2018-08-08 16:51 ` Reinette Chatre
2018-08-08 7:51 ` Peter Zijlstra
2018-08-08 17:33 ` Reinette Chatre
2018-08-10 16:25 ` Reinette Chatre
2018-08-10 17:52 ` Reinette Chatre
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