* [PATCH V2 0/2] perf: Add Tremont support @ 2019-04-10 18:57 kan.liang 2019-04-10 18:57 ` [PATCH V2 1/2] perf/x86/intel: Fix the checking for instruction event kan.liang 2019-04-10 18:57 ` [PATCH V2 2/2] perf/x86/intel: Add Tremont core PMU support kan.liang 0 siblings, 2 replies; 8+ messages in thread From: kan.liang @ 2019-04-10 18:57 UTC (permalink / raw) To: peterz, mingo, linux-kernel Cc: tglx, acme, jolsa, eranian, alexander.shishkin, ak, Kan Liang From: Kan Liang <kan.liang@linux.intel.com> The patch series intends to add Tremont support for Linux perf. The patch series is on top of Icelake V5 patch series (with Peter's cleanup patch). https://lkml.org/lkml/2019/4/8/630 PATCH 1: A fix for Icelake V5 patch series (with Peter's cleanup patch). It can be merged back into "Subject: perf/x86/intel: Add Icelake support" PATCH 2: Tremont core PMU support. Changes since V1: - The previous patch "perf/x86/intel: Support adaptive PEBS for fixed counters" will be merged back. - New patch to fix the checking for instruction event. - Allow instruction:ppp on generic purpose counter 0 Kan Liang (2): perf/x86/intel: Fix the checking for instruction event perf/x86/intel: Add Tremont core PMU support arch/x86/events/intel/core.c | 96 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 95 insertions(+), 1 deletion(-) -- 2.7.4 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH V2 1/2] perf/x86/intel: Fix the checking for instruction event 2019-04-10 18:57 [PATCH V2 0/2] perf: Add Tremont support kan.liang @ 2019-04-10 18:57 ` kan.liang 2019-04-10 18:57 ` [PATCH V2 2/2] perf/x86/intel: Add Tremont core PMU support kan.liang 1 sibling, 0 replies; 8+ messages in thread From: kan.liang @ 2019-04-10 18:57 UTC (permalink / raw) To: peterz, mingo, linux-kernel Cc: tglx, acme, jolsa, eranian, alexander.shishkin, ak, Kan Liang From: Kan Liang <kan.liang@linux.intel.com> Some bits must be masked before checking X86_CONFIG(.event=0xc0), e.g. ARCH_PERFMON_EVENTSEL_INT, ARCH_PERFMON_EVENTSEL_USR and ARCH_PERFMON_EVENTSEL_OS. Those bits will be set in hw_config(). Otherwise the condition will never be met. Other fields, e.g the INV, ANY, E, or CMASK fields are not allowed for the reduced Skid PEBS. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> --- New patch to fix a bug on top of Icelake V5 patch series (with Peter's cleanup patch). The patch may be merged back into: Subject: perf/x86/intel: Add Icelake support arch/x86/events/intel/core.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index f34d92b..34220ab 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3421,6 +3421,9 @@ hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, return c; } +#define EVENT_CONFIG(config) \ + (config & (X86_ALL_EVENT_FLAGS | INTEL_ARCH_EVENT_MASK)) + static struct event_constraint * icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, struct perf_event *event) @@ -3430,7 +3433,7 @@ icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx, * Force instruction:ppp in Fixed counter 0 */ if ((event->attr.precise_ip == 3) && - (event->hw.config == X86_CONFIG(.event=0xc0))) + (EVENT_CONFIG(event->hw.config) == X86_CONFIG(.event=0xc0))) return &fixed_counter0_constraint; return hsw_get_event_constraints(cpuc, idx, event); -- 2.7.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH V2 2/2] perf/x86/intel: Add Tremont core PMU support 2019-04-10 18:57 [PATCH V2 0/2] perf: Add Tremont support kan.liang 2019-04-10 18:57 ` [PATCH V2 1/2] perf/x86/intel: Fix the checking for instruction event kan.liang @ 2019-04-10 18:57 ` kan.liang 2019-04-11 9:06 ` Peter Zijlstra 2019-04-16 11:41 ` [tip:perf/core] " tip-bot for Kan Liang 1 sibling, 2 replies; 8+ messages in thread From: kan.liang @ 2019-04-10 18:57 UTC (permalink / raw) To: peterz, mingo, linux-kernel Cc: tglx, acme, jolsa, eranian, alexander.shishkin, ak, Kan Liang From: Kan Liang <kan.liang@linux.intel.com> Add perf core PMU support for Intel Tremont CPU. The init code is based on Goldmont plus. The generic purpose counter 0 and fixed counter 0 have less skid. Force :ppp events on generic purpose counter 0. Force instruction:ppp on generic purpose counter 0 and fixed counter 0. Updates LLC cache event table and OFFCORE_RESPONSE mask. The adaptive PEBS, which is already enabled on ICL, is also supported on Tremont. No extra codes required. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> --- Changes since v1: - Allow instruction:ppp on generic purpose counter 0 - Fix the checking for instruction event. arch/x86/events/intel/core.c | 91 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 34220ab..9f1e000 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -1856,6 +1856,45 @@ static __initconst const u64 glp_hw_cache_extra_regs }, }; +#define TNT_LOCAL_DRAM BIT_ULL(26) +#define TNT_DEMAND_READ GLM_DEMAND_DATA_RD +#define TNT_DEMAND_WRITE GLM_DEMAND_RFO +#define TNT_LLC_ACCESS GLM_ANY_RESPONSE +#define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ + SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) +#define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) + +static __initconst const u64 tnt_hw_cache_extra_regs + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { + [C(LL)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = TNT_DEMAND_READ| + TNT_LLC_ACCESS, + [C(RESULT_MISS)] = TNT_DEMAND_READ| + TNT_LLC_MISS, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| + TNT_LLC_ACCESS, + [C(RESULT_MISS)] = TNT_DEMAND_WRITE| + TNT_LLC_MISS, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = 0x0, + [C(RESULT_MISS)] = 0x0, + }, + }, +}; + +static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { + /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ + INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffffff9fffull, RSP_0), + INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xffffff9fffull, RSP_1), + EVENT_EXTRA_END +}; + #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ #define KNL_MCDRAM_LOCAL BIT_ULL(21) @@ -3403,6 +3442,9 @@ static struct event_constraint counter2_constraint = static struct event_constraint fixed_counter0_constraint = FIXED_EVENT_CONSTRAINT(0x00c0, 0); +static struct event_constraint fixed0_counter0_constraint = + INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); + static struct event_constraint * hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, struct perf_event *event) @@ -3454,6 +3496,29 @@ glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, return c; } +static struct event_constraint * +tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, + struct perf_event *event) +{ + struct event_constraint *c; + + /* + * :ppp means to do reduced skid PEBS, + * which is available on PMC0 and fixed counter 0. + */ + if (event->attr.precise_ip == 3) { + /* Force instruction:ppp on PMC0 and Fixed counter 0 */ + if (EVENT_CONFIG(event->hw.config) == X86_CONFIG(.event=0xc0)) + return &fixed0_counter0_constraint; + + return &counter0_constraint; + } + + c = intel_get_event_constraints(cpuc, idx, event); + + return c; +} + static bool allow_tsx_force_abort = true; static struct event_constraint * @@ -4533,6 +4598,32 @@ __init int intel_pmu_init(void) name = "goldmont_plus"; break; + case INTEL_FAM6_ATOM_TREMONT_X: + x86_pmu.late_ack = true; + memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, + sizeof(hw_cache_event_ids)); + memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, + sizeof(hw_cache_extra_regs)); + hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; + + intel_pmu_lbr_init_skl(); + + x86_pmu.event_constraints = intel_slm_event_constraints; + x86_pmu.extra_regs = intel_tnt_extra_regs; + /* + * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS + * for precise cycles. + */ + x86_pmu.pebs_aliases = NULL; + x86_pmu.pebs_prec_dist = true; + x86_pmu.lbr_pt_coexist = true; + x86_pmu.flags |= PMU_FL_HAS_RSP_1; + x86_pmu.get_event_constraints = tnt_get_event_constraints; + extra_attr = slm_format_attr; + pr_cont("Tremont events, "); + name = "Tremont"; + break; + case INTEL_FAM6_WESTMERE: case INTEL_FAM6_WESTMERE_EP: case INTEL_FAM6_WESTMERE_EX: -- 2.7.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH V2 2/2] perf/x86/intel: Add Tremont core PMU support 2019-04-10 18:57 ` [PATCH V2 2/2] perf/x86/intel: Add Tremont core PMU support kan.liang @ 2019-04-11 9:06 ` Peter Zijlstra 2019-04-11 13:30 ` Liang, Kan 2019-04-16 11:41 ` [tip:perf/core] " tip-bot for Kan Liang 1 sibling, 1 reply; 8+ messages in thread From: Peter Zijlstra @ 2019-04-11 9:06 UTC (permalink / raw) To: kan.liang Cc: mingo, linux-kernel, tglx, acme, jolsa, eranian, alexander.shishkin, ak On Wed, Apr 10, 2019 at 11:57:09AM -0700, kan.liang@linux.intel.com wrote: > +static struct event_constraint * > +tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, > + struct perf_event *event) That 'tnt' still cracks me up, I keep seeing explosions. > +{ > + struct event_constraint *c; > + > + /* > + * :ppp means to do reduced skid PEBS, > + * which is available on PMC0 and fixed counter 0. > + */ > + if (event->attr.precise_ip == 3) { > + /* Force instruction:ppp on PMC0 and Fixed counter 0 */ > + if (EVENT_CONFIG(event->hw.config) == X86_CONFIG(.event=0xc0)) > + return &fixed0_counter0_constraint; > + > + return &counter0_constraint; > + } > + > + c = intel_get_event_constraints(cpuc, idx, event); > + > + return c; > +} I changed that like so: --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3508,7 +3508,7 @@ tnt_get_event_constraints(struct cpu_hw_ */ if (event->attr.precise_ip == 3) { /* Force instruction:ppp on PMC0 and Fixed counter 0 */ - if (EVENT_CONFIG(event->hw.config) == X86_CONFIG(.event=0xc0)) + if (constraint_match(&fixed_counter0_constraint, event->hw.config)) return &fixed0_counter0_constraint; return &counter0_constraint; And maybe we should do: s/fixed_counter0_constraint/fixed0_constraint/' Those two constraints only differ by a single character, that's bad for reading comprehension. In fact, I just did that too. ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH V2 2/2] perf/x86/intel: Add Tremont core PMU support 2019-04-11 9:06 ` Peter Zijlstra @ 2019-04-11 13:30 ` Liang, Kan 2019-04-11 13:33 ` Peter Zijlstra 0 siblings, 1 reply; 8+ messages in thread From: Liang, Kan @ 2019-04-11 13:30 UTC (permalink / raw) To: Peter Zijlstra Cc: mingo, linux-kernel, tglx, acme, jolsa, eranian, alexander.shishkin, ak On 4/11/2019 5:06 AM, Peter Zijlstra wrote: > On Wed, Apr 10, 2019 at 11:57:09AM -0700, kan.liang@linux.intel.com wrote: >> +static struct event_constraint * >> +tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, >> + struct perf_event *event) > > That 'tnt' still cracks me up, I keep seeing explosions. > Boom! >> +{ >> + struct event_constraint *c; >> + >> + /* >> + * :ppp means to do reduced skid PEBS, >> + * which is available on PMC0 and fixed counter 0. >> + */ >> + if (event->attr.precise_ip == 3) { >> + /* Force instruction:ppp on PMC0 and Fixed counter 0 */ >> + if (EVENT_CONFIG(event->hw.config) == X86_CONFIG(.event=0xc0)) >> + return &fixed0_counter0_constraint; >> + >> + return &counter0_constraint; >> + } >> + >> + c = intel_get_event_constraints(cpuc, idx, event); >> + >> + return c; >> +} > > I changed that like so: > > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -3508,7 +3508,7 @@ tnt_get_event_constraints(struct cpu_hw_ > */ > if (event->attr.precise_ip == 3) { > /* Force instruction:ppp on PMC0 and Fixed counter 0 */ > - if (EVENT_CONFIG(event->hw.config) == X86_CONFIG(.event=0xc0)) > + if (constraint_match(&fixed_counter0_constraint, event->hw.config)) Should be if (constraint_match(&fixed0_counter0_constraint, event->hw.config)) > return &fixed0_counter0_constraint; > > return &counter0_constraint; > > > And maybe we should do: > > s/fixed_counter0_constraint/fixed0_constraint/' > Yes, definitely. It has already caused confusions. :) Thanks, Kan > Those two constraints only differ by a single character, that's bad for > reading comprehension. > > In fact, I just did that too. > ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH V2 2/2] perf/x86/intel: Add Tremont core PMU support 2019-04-11 13:30 ` Liang, Kan @ 2019-04-11 13:33 ` Peter Zijlstra 2019-04-11 14:13 ` Liang, Kan 0 siblings, 1 reply; 8+ messages in thread From: Peter Zijlstra @ 2019-04-11 13:33 UTC (permalink / raw) To: Liang, Kan Cc: mingo, linux-kernel, tglx, acme, jolsa, eranian, alexander.shishkin, ak On Thu, Apr 11, 2019 at 09:30:10AM -0400, Liang, Kan wrote: > > I changed that like so: > > > > --- a/arch/x86/events/intel/core.c > > +++ b/arch/x86/events/intel/core.c > > @@ -3508,7 +3508,7 @@ tnt_get_event_constraints(struct cpu_hw_ > > */ > > if (event->attr.precise_ip == 3) { > > /* Force instruction:ppp on PMC0 and Fixed counter 0 */ > > - if (EVENT_CONFIG(event->hw.config) == X86_CONFIG(.event=0xc0)) > > + if (constraint_match(&fixed_counter0_constraint, event->hw.config)) > > Should be > if (constraint_match(&fixed0_counter0_constraint, event->hw.config)) No, because fixed0_counter0_constraint doesn't set an event. The logic as I proposed checks if it fits the fixed0 constraint, and if so, allows f0-c0, otherwise only c0. > > return &fixed0_counter0_constraint; > > return &counter0_constraint; > > ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH V2 2/2] perf/x86/intel: Add Tremont core PMU support 2019-04-11 13:33 ` Peter Zijlstra @ 2019-04-11 14:13 ` Liang, Kan 0 siblings, 0 replies; 8+ messages in thread From: Liang, Kan @ 2019-04-11 14:13 UTC (permalink / raw) To: Peter Zijlstra Cc: mingo, linux-kernel, tglx, acme, jolsa, eranian, alexander.shishkin, ak On 4/11/2019 9:33 AM, Peter Zijlstra wrote: > On Thu, Apr 11, 2019 at 09:30:10AM -0400, Liang, Kan wrote: > >>> I changed that like so: >>> >>> --- a/arch/x86/events/intel/core.c >>> +++ b/arch/x86/events/intel/core.c >>> @@ -3508,7 +3508,7 @@ tnt_get_event_constraints(struct cpu_hw_ >>> */ >>> if (event->attr.precise_ip == 3) { >>> /* Force instruction:ppp on PMC0 and Fixed counter 0 */ >>> - if (EVENT_CONFIG(event->hw.config) == X86_CONFIG(.event=0xc0)) >>> + if (constraint_match(&fixed_counter0_constraint, event->hw.config)) >> >> Should be >> if (constraint_match(&fixed0_counter0_constraint, event->hw.config)) > > No, because fixed0_counter0_constraint doesn't set an event. > Right, it will mistakenly allow other events to use fixed0. > The logic as I proposed checks if it fits the fixed0 constraint, and if > so, allows f0-c0, otherwise only c0. It looks good. Thanks, Kan > >>> return &fixed0_counter0_constraint; >>> return &counter0_constraint; >>> ^ permalink raw reply [flat|nested] 8+ messages in thread
* [tip:perf/core] perf/x86/intel: Add Tremont core PMU support 2019-04-10 18:57 ` [PATCH V2 2/2] perf/x86/intel: Add Tremont core PMU support kan.liang 2019-04-11 9:06 ` Peter Zijlstra @ 2019-04-16 11:41 ` tip-bot for Kan Liang 1 sibling, 0 replies; 8+ messages in thread From: tip-bot for Kan Liang @ 2019-04-16 11:41 UTC (permalink / raw) To: linux-tip-commits Cc: mingo, eranian, alexander.shishkin, tglx, linux-kernel, peterz, hpa, kan.liang, torvalds, jolsa, acme, vincent.weaver Commit-ID: 6daeb8737f8a93c6d3a3ae57e23dd3dbe8b239da Gitweb: https://git.kernel.org/tip/6daeb8737f8a93c6d3a3ae57e23dd3dbe8b239da Author: Kan Liang <kan.liang@linux.intel.com> AuthorDate: Wed, 10 Apr 2019 11:57:09 -0700 Committer: Ingo Molnar <mingo@kernel.org> CommitDate: Tue, 16 Apr 2019 12:26:19 +0200 perf/x86/intel: Add Tremont core PMU support Add perf core PMU support for Intel Tremont CPU. The init code is based on Goldmont plus. The generic purpose counter 0 and fixed counter 0 have less skid. Force :ppp events on generic purpose counter 0. Force instruction:ppp on generic purpose counter 0 and fixed counter 0. Updates LLC cache event table and OFFCORE_RESPONSE mask. Adaptive PEBS, which is already enabled on ICL, is also supported on Tremont. No extra code required. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: acme@kernel.org Cc: jolsa@kernel.org Link: https://lkml.kernel.org/r/1554922629-126287-3-git-send-email-kan.liang@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org> --- arch/x86/events/intel/core.c | 91 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 156c6ae53d3c..4b4dac089635 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -1856,6 +1856,45 @@ static __initconst const u64 glp_hw_cache_extra_regs }, }; +#define TNT_LOCAL_DRAM BIT_ULL(26) +#define TNT_DEMAND_READ GLM_DEMAND_DATA_RD +#define TNT_DEMAND_WRITE GLM_DEMAND_RFO +#define TNT_LLC_ACCESS GLM_ANY_RESPONSE +#define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \ + SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM) +#define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM) + +static __initconst const u64 tnt_hw_cache_extra_regs + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { + [C(LL)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = TNT_DEMAND_READ| + TNT_LLC_ACCESS, + [C(RESULT_MISS)] = TNT_DEMAND_READ| + TNT_LLC_MISS, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE| + TNT_LLC_ACCESS, + [C(RESULT_MISS)] = TNT_DEMAND_WRITE| + TNT_LLC_MISS, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = 0x0, + [C(RESULT_MISS)] = 0x0, + }, + }, +}; + +static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { + /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ + INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffffff9fffull, RSP_0), + INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xffffff9fffull, RSP_1), + EVENT_EXTRA_END +}; + #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ #define KNL_MCDRAM_LOCAL BIT_ULL(21) @@ -3406,6 +3445,9 @@ static struct event_constraint counter2_constraint = static struct event_constraint fixed0_constraint = FIXED_EVENT_CONSTRAINT(0x00c0, 0); +static struct event_constraint fixed0_counter0_constraint = + INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL); + static struct event_constraint * hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx, struct perf_event *event) @@ -3454,6 +3496,29 @@ glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, return c; } +static struct event_constraint * +tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, + struct perf_event *event) +{ + struct event_constraint *c; + + /* + * :ppp means to do reduced skid PEBS, + * which is available on PMC0 and fixed counter 0. + */ + if (event->attr.precise_ip == 3) { + /* Force instruction:ppp on PMC0 and Fixed counter 0 */ + if (constraint_match(&fixed0_constraint, event->hw.config)) + return &fixed0_counter0_constraint; + + return &counter0_constraint; + } + + c = intel_get_event_constraints(cpuc, idx, event); + + return c; +} + static bool allow_tsx_force_abort = true; static struct event_constraint * @@ -4585,6 +4650,32 @@ __init int intel_pmu_init(void) name = "goldmont_plus"; break; + case INTEL_FAM6_ATOM_TREMONT_X: + x86_pmu.late_ack = true; + memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, + sizeof(hw_cache_event_ids)); + memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs, + sizeof(hw_cache_extra_regs)); + hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; + + intel_pmu_lbr_init_skl(); + + x86_pmu.event_constraints = intel_slm_event_constraints; + x86_pmu.extra_regs = intel_tnt_extra_regs; + /* + * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS + * for precise cycles. + */ + x86_pmu.pebs_aliases = NULL; + x86_pmu.pebs_prec_dist = true; + x86_pmu.lbr_pt_coexist = true; + x86_pmu.flags |= PMU_FL_HAS_RSP_1; + x86_pmu.get_event_constraints = tnt_get_event_constraints; + extra_attr = slm_format_attr; + pr_cont("Tremont events, "); + name = "Tremont"; + break; + case INTEL_FAM6_WESTMERE: case INTEL_FAM6_WESTMERE_EP: case INTEL_FAM6_WESTMERE_EX: ^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-04-16 11:41 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-04-10 18:57 [PATCH V2 0/2] perf: Add Tremont support kan.liang 2019-04-10 18:57 ` [PATCH V2 1/2] perf/x86/intel: Fix the checking for instruction event kan.liang 2019-04-10 18:57 ` [PATCH V2 2/2] perf/x86/intel: Add Tremont core PMU support kan.liang 2019-04-11 9:06 ` Peter Zijlstra 2019-04-11 13:30 ` Liang, Kan 2019-04-11 13:33 ` Peter Zijlstra 2019-04-11 14:13 ` Liang, Kan 2019-04-16 11:41 ` [tip:perf/core] " tip-bot for Kan Liang
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