From: Rob Herring <robh@kernel.org>
To: Robert Hancock <robert.hancock@calian.com>
Cc: radhey.shyam.pandey@xilinx.com, davem@davemloft.net,
kuba@kernel.org, netdev@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH net-next v3 v3 1/2] dt-bindings: net: xilinx_axienet: Document additional clocks
Date: Wed, 24 Mar 2021 11:08:06 -0600 [thread overview]
Message-ID: <20210324170806.GA3252450@robh.at.kernel.org> (raw)
In-Reply-To: <20210312195214.4002847-2-robert.hancock@calian.com>
On Fri, Mar 12, 2021 at 01:52:13PM -0600, Robert Hancock wrote:
> Update DT bindings to describe all of the clocks that the axienet
> driver will now be able to make use of.
>
> Signed-off-by: Robert Hancock <robert.hancock@calian.com>
> ---
> .../bindings/net/xilinx_axienet.txt | 25 ++++++++++++++-----
> 1 file changed, 19 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.txt b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
> index 2cd452419ed0..b8e4894bc634 100644
> --- a/Documentation/devicetree/bindings/net/xilinx_axienet.txt
> +++ b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
> @@ -42,11 +42,23 @@ Optional properties:
> support both 1000BaseX and SGMII modes. If set, the phy-mode
> should be set to match the mode selected on core reset (i.e.
> by the basex_or_sgmii core input line).
> -- clocks : AXI bus clock for the device. Refer to common clock bindings.
> - Used to calculate MDIO clock divisor. If not specified, it is
> - auto-detected from the CPU clock (but only on platforms where
> - this is possible). New device trees should specify this - the
> - auto detection is only for backward compatibility.
> +- clock-names: Tuple listing input clock names. Possible clocks:
> + s_axi_lite_clk: Clock for AXI register slave interface
> + axis_clk: AXI4-Stream clock for TXD RXD TXC and RXS interfaces
> + ref_clk: Ethernet reference clock, used by signal delay
> + primitives and transceivers
> + mgt_clk: MGT reference clock (used by optional internal
> + PCS/PMA PHY)
'_clk' is redundant.
> +
> + Note that if s_axi_lite_clk is not specified by name, the
> + first clock of any name is used for this. If that is also not
> + specified, the clock rate is auto-detected from the CPU clock
> + (but only on platforms where this is possible). New device
> + trees should specify all applicable clocks by name - the
> + fallbacks to an unnamed clock or to CPU clock are only for
> + backward compatibility.
> +- clocks: Phandles to input clocks matching clock-names. Refer to common
> + clock bindings.
> - axistream-connected: Reference to another node which contains the resources
> for the AXI DMA controller used by this device.
> If this is specified, the DMA-related resources from that
> @@ -62,7 +74,8 @@ Example:
> device_type = "network";
> interrupt-parent = <µblaze_0_axi_intc>;
> interrupts = <2 0 1>;
> - clocks = <&axi_clk>;
> + clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
> + clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
> phy-mode = "mii";
> reg = <0x40c00000 0x40000 0x50c00000 0x40000>;
> xlnx,rxcsum = <0x2>;
> --
> 2.27.0
>
next prev parent reply other threads:[~2021-03-24 17:10 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-12 19:52 [PATCH net-next v3 v3 0/2] axienet clock additions Robert Hancock
2021-03-12 19:52 ` [PATCH net-next v3 v3 1/2] dt-bindings: net: xilinx_axienet: Document additional clocks Robert Hancock
2021-03-24 17:08 ` Rob Herring [this message]
2021-03-24 17:19 ` Robert Hancock
2021-03-25 13:54 ` Rob Herring
2021-03-12 19:52 ` [PATCH net-next v3 v3 2/2] net: axienet: Enable more clocks Robert Hancock
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