Re: [PATCH net-next v3 v3 1/2] dt-bindings: net: xilinx_axienet: Document additional clocks

[Robert Hancock <robert.hancock@calian.com>]

On Wed, 2021-03-24 at 11:08 -0600, Rob Herring wrote:
> On Fri, Mar 12, 2021 at 01:52:13PM -0600, Robert Hancock wrote:
> > Update DT bindings to describe all of the clocks that the axienet
> > driver will now be able to make use of.
> > 
> > Signed-off-by: Robert Hancock <robert.hancock@calian.com>
> > ---
> >  .../bindings/net/xilinx_axienet.txt           | 25 ++++++++++++++-----
> >  1 file changed, 19 insertions(+), 6 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.txt
> > b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
> > index 2cd452419ed0..b8e4894bc634 100644
> > --- a/Documentation/devicetree/bindings/net/xilinx_axienet.txt
> > +++ b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
> > @@ -42,11 +42,23 @@ Optional properties:
> >  		  support both 1000BaseX and SGMII modes. If set, the phy-mode
> >  		  should be set to match the mode selected on core reset (i.e.
> >  		  by the basex_or_sgmii core input line).
> > -- clocks	: AXI bus clock for the device. Refer to common clock bindings.
> > -		  Used to calculate MDIO clock divisor. If not specified, it is
> > -		  auto-detected from the CPU clock (but only on platforms where
> > -		  this is possible). New device trees should specify this - the
> > -		  auto detection is only for backward compatibility.
> > +- clock-names: 	  Tuple listing input clock names. Possible clocks:
> > +		  s_axi_lite_clk: Clock for AXI register slave interface
> > +		  axis_clk: AXI4-Stream clock for TXD RXD TXC and RXS
> > interfaces
> > +		  ref_clk: Ethernet reference clock, used by signal delay
> > +			   primitives and transceivers
> > +		  mgt_clk: MGT reference clock (used by optional internal
> > +			   PCS/PMA PHY)
> 
> '_clk' is redundant.

True, but there are existing device trees which already referenced these names
because those are what was used by the Xilinx version of this driver and hence
the Xilinx device tree generation software. So for compatibility I think we are
kind of stuck with those names..

> 
> > +
> > +		  Note that if s_axi_lite_clk is not specified by name, the
> > +		  first clock of any name is used for this. If that is also not
> > +		  specified, the clock rate is auto-detected from the CPU clock
> > +		  (but only on platforms where this is possible). New device
> > +		  trees should specify all applicable clocks by name - the
> > +		  fallbacks to an unnamed clock or to CPU clock are only for
> > +		  backward compatibility.
> > +- clocks: 	  Phandles to input clocks matching clock-names. Refer to
> > common
> > +		  clock bindings.
> >  - axistream-connected: Reference to another node which contains the
> > resources
> >  		       for the AXI DMA controller used by this device.
> >  		       If this is specified, the DMA-related resources from
> > that
> > @@ -62,7 +74,8 @@ Example:
> >  		device_type = "network";
> >  		interrupt-parent = <&microblaze_0_axi_intc>;
> >  		interrupts = <2 0 1>;
> > -		clocks = <&axi_clk>;
> > +		clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk",
> > "mgt_clk";
> > +		clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>,
> > <&mgt_clk>;
> >  		phy-mode = "mii";
> >  		reg = <0x40c00000 0x40000 0x50c00000 0x40000>;
> >  		xlnx,rxcsum = <0x2>;
> > -- 
> > 2.27.0
> > 
-- 
Robert Hancock
Senior Hardware Designer, Calian Advanced Technologies
www.calian.com