[PATCH 0/9] Add Renesas RZ/V2M Ethernet support

[PATCH 0/9] Add Renesas RZ/V2M Ethernet support

[Phil Edworthy]

The RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB, though
some small parts are the same as R-Car Gen2.
Other differences are:
* It has separate data (DI), error (Line 1) and management (Line 2) irqs
  rather than one irq for all three.
* Instead of using the High-speed peripheral bus clock for gPTP, it has
  a separate gPTP reference clock.

The dts patches depend on v4 of the following patch set:
"Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support"

Phil Edworthy (9):
  clk: renesas: r9a09g011: Add eth clock and reset entries
  dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC
  ravb: Separate use of GIC reg for PTME from multi_irqs
  ravb: Separate handling of irq enable/disable regs into feature
  ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs
  ravb: Use separate clock for gPTP
  ravb: Add support for RZ/V2M
  arm64: dts: renesas: r9a09g011: Add ethernet nodes
  arm64: dts: renesas: rzv2m evk: Enable ethernet

 .../bindings/net/renesas,etheravb.yaml        | 82 ++++++++++++-----
 .../boot/dts/renesas/r9a09g011-v2mevk2.dts    | 14 +++
 arch/arm64/boot/dts/renesas/r9a09g011.dtsi    | 51 +++++++++++
 drivers/clk/renesas/r9a09g011-cpg.c           | 14 +--
 drivers/net/ethernet/renesas/ravb.h           |  7 ++
 drivers/net/ethernet/renesas/ravb_main.c      | 89 +++++++++++++++++--
 drivers/net/ethernet/renesas/ravb_ptp.c       |  4 +-
 7 files changed, 228 insertions(+), 33 deletions(-)

-- 
2.32.0

[PATCH 2/9] dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC

[Phil Edworthy]

Document the Ethernet AVB IP found on RZ/V2M SoC.
It includes the Ethernet controller (E-MAC) and Dedicated Direct memory
access controller (DMAC) for transferring transmitted Ethernet frames
to and received Ethernet frames from respective storage areas in the
URAM at high speed.
The AVB-DMAC is compliant with IEEE 802.1BA, IEEE 802.1AS timing and
synchronization protocol, IEEE 802.1Qav real-time transfer, and the
IEEE 802.1Qat stream reservation protocol.

R-Car has a pair of combined interrupt lines:
 ch22 = Line0_DiA | Line1_A | Line2_A
 ch23 = Line0_DiB | Line1_B | Line2_B
Line0 for descriptor interrupts.
Line1 for error related interrupts (which we call err_a and err_b).
Line2 for management and gPTP related interrupts (mgmt_a and mgmt_b).

RZ/V2M hardware has separate interrupt lines for each of these, but
we keep the "ch22" name for Line0_DiA. We also keep the "ch24" name
for the Line3 (MAC) interrupt.

It has 3 clocks; the main AXI clock, the AMBA CHI clock and a gPTP
reference clock.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../bindings/net/renesas,etheravb.yaml        | 82 ++++++++++++++-----
 1 file changed, 61 insertions(+), 21 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
index ee2ccacc39ff..6c5172ff2b18 100644
--- a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
+++ b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
@@ -43,6 +43,11 @@ properties:
               - renesas,etheravb-r8a779a0     # R-Car V3U
           - const: renesas,etheravb-rcar-gen3 # R-Car Gen3 and RZ/G2
 
+      - items:
+          - enum:
+              - renesas,etheravb-r9a09g011 # RZ/V2M
+          - const: renesas,etheravb-rzv2m  # RZ/V2M compatible
+
       - items:
           - enum:
               - renesas,r9a07g043-gbeth # RZ/G2UL
@@ -160,16 +165,33 @@ allOf:
             - const: arp_ns
         rx-internal-delay-ps: false
     else:
-      properties:
-        interrupts:
-          minItems: 25
-          maxItems: 25
-        interrupt-names:
-          items:
-            pattern: '^ch[0-9]+$'
-      required:
-        - interrupt-names
-        - rx-internal-delay-ps
+      if:
+        properties:
+          compatible:
+            contains:
+              const: renesas,etheravb-rzv2m
+      then:
+        properties:
+          interrupts:
+            minItems: 29
+            maxItems: 29
+          interrupt-names:
+            items:
+              pattern: '^(ch[0-9]+)|dib|err_a|err_b|mgmt_a|mgmt_b$'
+          rx-internal-delay-ps: false
+        required:
+          - interrupt-names
+      else:
+        properties:
+          interrupts:
+            minItems: 25
+            maxItems: 25
+          interrupt-names:
+            items:
+              pattern: '^ch[0-9]+$'
+        required:
+          - interrupt-names
+          - rx-internal-delay-ps
 
   - if:
       properties:
@@ -231,17 +253,35 @@ allOf:
             - const: chi
             - const: refclk
     else:
-      properties:
-        clocks:
-          minItems: 1
-          items:
-            - description: AVB functional clock
-            - description: Optional TXC reference clock
-        clock-names:
-          minItems: 1
-          items:
-            - const: fck
-            - const: refclk
+      if:
+        properties:
+          compatible:
+            contains:
+              const: renesas,etheravb-rzv2m
+      then:
+        properties:
+          clocks:
+            items:
+              - description: Main clock
+              - description: Coherent Hub Interface clock
+              - description: gPTP reference clock
+          clock-names:
+            items:
+              - const: axi
+              - const: chi
+              - const: gptp
+      else:
+        properties:
+          clocks:
+            minItems: 1
+            items:
+              - description: AVB functional clock
+              - description: Optional TXC reference clock
+          clock-names:
+            minItems: 1
+            items:
+              - const: fck
+              - const: refclk
 
 additionalProperties: false
 
-- 
2.32.0

[PATCH 3/9] ravb: Separate use of GIC reg for PTME from multi_irqs

[Phil Edworthy]

When the HW has a single interrupt, the driver currently uses the
PTME (Presentation Time Match Enable) bit in the GIC register to
enable/disable the PTM irq. Otherwise, it uses the GIE/GID registers.

However, other SoCs, e.g. RZ/V2M, have multiple irqs and use the GIC
register PTME bit, so separate it out as it's own feature.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/net/ethernet/renesas/ravb.h      | 1 +
 drivers/net/ethernet/renesas/ravb_main.c | 1 +
 drivers/net/ethernet/renesas/ravb_ptp.c  | 4 ++--
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
index 08062d73df10..15aa09d93ff0 100644
--- a/drivers/net/ethernet/renesas/ravb.h
+++ b/drivers/net/ethernet/renesas/ravb.h
@@ -1029,6 +1029,7 @@ struct ravb_hw_info {
 	unsigned multi_irqs:1;		/* AVB-DMAC and E-MAC has multiple irqs */
 	unsigned gptp:1;		/* AVB-DMAC has gPTP support */
 	unsigned ccc_gac:1;		/* AVB-DMAC has gPTP support active in config mode */
+	unsigned gptp_ptm_gic:1;	/* gPTP enables Presentation Time Match irq via GIC */
 	unsigned nc_queues:1;		/* AVB-DMAC has RX and TX NC queues */
 	unsigned magic_pkt:1;		/* E-MAC supports magic packet detection */
 	unsigned half_duplex:1;		/* E-MAC supports half duplex mode */
diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index 525d66f71f02..de2792c03099 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -2434,6 +2434,7 @@ static const struct ravb_hw_info ravb_gen2_hw_info = {
 	.rx_max_buf_size = SZ_2K,
 	.aligned_tx = 1,
 	.gptp = 1,
+	.gptp_ptm_gic = 1,
 	.nc_queues = 1,
 	.magic_pkt = 1,
 };
diff --git a/drivers/net/ethernet/renesas/ravb_ptp.c b/drivers/net/ethernet/renesas/ravb_ptp.c
index c099656dd75b..f8e75dddcaf1 100644
--- a/drivers/net/ethernet/renesas/ravb_ptp.c
+++ b/drivers/net/ethernet/renesas/ravb_ptp.c
@@ -254,7 +254,7 @@ static int ravb_ptp_perout(struct ptp_clock_info *ptp,
 		error = ravb_ptp_update_compare(priv, (u32)start_ns);
 		if (!error) {
 			/* Unmask interrupt */
-			if (!info->multi_irqs)
+			if (info->gptp_ptm_gic)
 				ravb_modify(ndev, GIC, GIC_PTME, GIC_PTME);
 			else
 				ravb_write(ndev, GIE_PTMS0, GIE);
@@ -266,7 +266,7 @@ static int ravb_ptp_perout(struct ptp_clock_info *ptp,
 		perout->period = 0;
 
 		/* Mask interrupt */
-		if (!info->multi_irqs)
+		if (info->gptp_ptm_gic)
 			ravb_modify(ndev, GIC, GIC_PTME, 0);
 		else
 			ravb_write(ndev, GID_PTMD0, GID);
-- 
2.32.0

[PATCH 4/9] ravb: Separate handling of irq enable/disable regs into feature

[Phil Edworthy]

Currently, when the HW has a single interrupt, the driver uses the
TIC, RIC0 registers to enable and disable RX/TX interrupts. When
the HW has multiple interrupts, it uses the TIE, TID, RIE0, RID0
registers.

However, other devices, e.g. RZ/V2M, have multiple irqs and use
the TIC, RIC0 registers.
Therefore, split this into a separate feature.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/net/ethernet/renesas/ravb.h      | 1 +
 drivers/net/ethernet/renesas/ravb_main.c | 5 +++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
index 15aa09d93ff0..67a240665cd2 100644
--- a/drivers/net/ethernet/renesas/ravb.h
+++ b/drivers/net/ethernet/renesas/ravb.h
@@ -1027,6 +1027,7 @@ struct ravb_hw_info {
 	unsigned tx_counters:1;		/* E-MAC has TX counters */
 	unsigned carrier_counters:1;	/* E-MAC has carrier counters */
 	unsigned multi_irqs:1;		/* AVB-DMAC and E-MAC has multiple irqs */
+	unsigned irq_en_dis_regs:1;	/* Has separate irq enable and disable regs */
 	unsigned gptp:1;		/* AVB-DMAC has gPTP support */
 	unsigned ccc_gac:1;		/* AVB-DMAC has gPTP support active in config mode */
 	unsigned gptp_ptm_gic:1;	/* gPTP enables Presentation Time Match irq via GIC */
diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index de2792c03099..d0b9688074ca 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -1124,7 +1124,7 @@ static bool ravb_queue_interrupt(struct net_device *ndev, int q)
 	if (((ris0 & ric0) & BIT(q)) || ((tis  & tic)  & BIT(q))) {
 		if (napi_schedule_prep(&priv->napi[q])) {
 			/* Mask RX and TX interrupts */
-			if (!info->multi_irqs) {
+			if (!info->irq_en_dis_regs) {
 				ravb_write(ndev, ric0 & ~BIT(q), RIC0);
 				ravb_write(ndev, tic & ~BIT(q), TIC);
 			} else {
@@ -1306,7 +1306,7 @@ static int ravb_poll(struct napi_struct *napi, int budget)
 
 	/* Re-enable RX/TX interrupts */
 	spin_lock_irqsave(&priv->lock, flags);
-	if (!info->multi_irqs) {
+	if (!info->irq_en_dis_regs) {
 		ravb_modify(ndev, RIC0, mask, mask);
 		ravb_modify(ndev, TIC,  mask, mask);
 	} else {
@@ -2410,6 +2410,7 @@ static const struct ravb_hw_info ravb_gen3_hw_info = {
 	.internal_delay = 1,
 	.tx_counters = 1,
 	.multi_irqs = 1,
+	.irq_en_dis_regs = 1,
 	.ccc_gac = 1,
 	.nc_queues = 1,
 	.magic_pkt = 1,
-- 
2.32.0

[PATCH 5/9] ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs

[Phil Edworthy]

R-Car has a combined interrupt line, ch22 = Line0_DiA | Line1_A | Line2_A.
RZ/V2M has separate interrupt lines for each of these, so add a feature
that allows the driver to get these interrupts and call the common handler.

We keep the "ch22" name for Line0_DiA and "ch24" for Line3 interrupts to
keep the code simple.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/net/ethernet/renesas/ravb.h      |  3 ++
 drivers/net/ethernet/renesas/ravb_main.c | 41 ++++++++++++++++++++++--
 2 files changed, 42 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
index 67a240665cd2..73976a392457 100644
--- a/drivers/net/ethernet/renesas/ravb.h
+++ b/drivers/net/ethernet/renesas/ravb.h
@@ -1028,6 +1028,7 @@ struct ravb_hw_info {
 	unsigned carrier_counters:1;	/* E-MAC has carrier counters */
 	unsigned multi_irqs:1;		/* AVB-DMAC and E-MAC has multiple irqs */
 	unsigned irq_en_dis_regs:1;	/* Has separate irq enable and disable regs */
+	unsigned err_mgmt_irqs:1;	/* Line1 (Err) and Line2 (Mgmt) irqs are separate */
 	unsigned gptp:1;		/* AVB-DMAC has gPTP support */
 	unsigned ccc_gac:1;		/* AVB-DMAC has gPTP support active in config mode */
 	unsigned gptp_ptm_gic:1;	/* gPTP enables Presentation Time Match irq via GIC */
@@ -1079,6 +1080,8 @@ struct ravb_private {
 	int msg_enable;
 	int speed;
 	int emac_irq;
+	int erra_irq;
+	int mgmta_irq;
 	int rx_irqs[NUM_RX_QUEUE];
 	int tx_irqs[NUM_TX_QUEUE];
 
diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index d0b9688074ca..f12a23b9c391 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -1798,12 +1798,23 @@ static int ravb_open(struct net_device *ndev)
 				      ndev, dev, "ch19:tx_nc");
 		if (error)
 			goto out_free_irq_nc_rx;
+
+		if (info->err_mgmt_irqs) {
+			error = ravb_hook_irq(priv->erra_irq, ravb_multi_interrupt,
+					      ndev, dev, "err_a");
+			if (error)
+				goto out_free_irq_nc_tx;
+			error = ravb_hook_irq(priv->mgmta_irq, ravb_multi_interrupt,
+					      ndev, dev, "mgmt_a");
+			if (error)
+				goto out_free_irq_erra;
+		}
 	}
 
 	/* Device init */
 	error = ravb_dmac_init(ndev);
 	if (error)
-		goto out_free_irq_nc_tx;
+		goto out_free_irq_mgmta;
 	ravb_emac_init(ndev);
 
 	/* Initialise PTP Clock driver */
@@ -1823,9 +1834,15 @@ static int ravb_open(struct net_device *ndev)
 	/* Stop PTP Clock driver */
 	if (info->gptp)
 		ravb_ptp_stop(ndev);
-out_free_irq_nc_tx:
+out_free_irq_mgmta:
 	if (!info->multi_irqs)
 		goto out_free_irq;
+	if (info->err_mgmt_irqs)
+		free_irq(priv->mgmta_irq, ndev);
+out_free_irq_erra:
+	if (info->err_mgmt_irqs)
+		free_irq(priv->erra_irq, ndev);
+out_free_irq_nc_tx:
 	free_irq(priv->tx_irqs[RAVB_NC], ndev);
 out_free_irq_nc_rx:
 	free_irq(priv->rx_irqs[RAVB_NC], ndev);
@@ -2167,6 +2184,10 @@ static int ravb_close(struct net_device *ndev)
 		free_irq(priv->rx_irqs[RAVB_BE], ndev);
 		free_irq(priv->emac_irq, ndev);
 	}
+	if (info->err_mgmt_irqs) {
+		free_irq(priv->erra_irq, ndev);
+		free_irq(priv->mgmta_irq, ndev);
+	}
 	free_irq(ndev->irq, ndev);
 
 	if (info->nc_queues)
@@ -2665,6 +2686,22 @@ static int ravb_probe(struct platform_device *pdev)
 		}
 	}
 
+	if (info->err_mgmt_irqs) {
+		irq = platform_get_irq_byname(pdev, "err_a");
+		if (irq < 0) {
+			error = irq;
+			goto out_release;
+		}
+		priv->erra_irq = irq;
+
+		irq = platform_get_irq_byname(pdev, "mgmt_a");
+		if (irq < 0) {
+			error = irq;
+			goto out_release;
+		}
+		priv->mgmta_irq = irq;
+	}
+
 	priv->clk = devm_clk_get(&pdev->dev, NULL);
 	if (IS_ERR(priv->clk)) {
 		error = PTR_ERR(priv->clk);
-- 
2.32.0

[PATCH 6/9] ravb: Use separate clock for gPTP

[Phil Edworthy]

RZ/V2M has a separate gPTP reference clock that is used when the
AVB-DMAC Mode Register (CCC) gPTP Clock Select (CSEL) bits are
set to "01: High-speed peripheral bus clock".
Therefore, add a feature that allows this clock to be used for
gPTP.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/net/ethernet/renesas/ravb.h      |  2 ++
 drivers/net/ethernet/renesas/ravb_main.c | 15 ++++++++++++++-
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
index 73976a392457..f8706897ea41 100644
--- a/drivers/net/ethernet/renesas/ravb.h
+++ b/drivers/net/ethernet/renesas/ravb.h
@@ -1032,6 +1032,7 @@ struct ravb_hw_info {
 	unsigned gptp:1;		/* AVB-DMAC has gPTP support */
 	unsigned ccc_gac:1;		/* AVB-DMAC has gPTP support active in config mode */
 	unsigned gptp_ptm_gic:1;	/* gPTP enables Presentation Time Match irq via GIC */
+	unsigned gptp_ref_clk:1;	/* gPTP has separate reference clock */
 	unsigned nc_queues:1;		/* AVB-DMAC has RX and TX NC queues */
 	unsigned magic_pkt:1;		/* E-MAC supports magic packet detection */
 	unsigned half_duplex:1;		/* E-MAC supports half duplex mode */
@@ -1043,6 +1044,7 @@ struct ravb_private {
 	void __iomem *addr;
 	struct clk *clk;
 	struct clk *refclk;
+	struct clk *gptp_clk;
 	struct mdiobb_ctrl mdiobb;
 	u32 num_rx_ring[NUM_RX_QUEUE];
 	u32 num_tx_ring[NUM_TX_QUEUE];
diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index f12a23b9c391..ded87cb51650 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -2496,11 +2496,15 @@ MODULE_DEVICE_TABLE(of, ravb_match_table);
 static int ravb_set_gti(struct net_device *ndev)
 {
 	struct ravb_private *priv = netdev_priv(ndev);
+	const struct ravb_hw_info *info = priv->info;
 	struct device *dev = ndev->dev.parent;
 	unsigned long rate;
 	uint64_t inc;
 
-	rate = clk_get_rate(priv->clk);
+	if (info->gptp_ref_clk)
+		rate = clk_get_rate(priv->gptp_clk);
+	else
+		rate = clk_get_rate(priv->clk);
 	if (!rate)
 		return -EINVAL;
 
@@ -2715,6 +2719,15 @@ static int ravb_probe(struct platform_device *pdev)
 	}
 	clk_prepare_enable(priv->refclk);
 
+	if (info->gptp_ref_clk) {
+		priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp");
+		if (IS_ERR(priv->gptp_clk)) {
+			error = PTR_ERR(priv->gptp_clk);
+			goto out_release;
+		}
+		clk_prepare_enable(priv->gptp_clk);
+	}
+
 	ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
 	ndev->min_mtu = ETH_MIN_MTU;
 
-- 
2.32.0

[PATCH 7/9] ravb: Add support for RZ/V2M

[Phil Edworthy]

RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB, though
some small parts are the same as R-Car Gen2.
Other differences are:
* It has separate data (DI), error (Line 1) and management (Line 2) irqs
  rather than one irq for all three.
* Instead of using the High-speed peripheral bus clock for gPTP, it has a
  separate gPTP reference clock.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Note: gPTP was tested using an RZ/V2M EVK and an R-Car M3N Salvator-XS
board, connected with a Summit X440 AVB switch, using ptp4l.
---
 drivers/net/ethernet/renesas/ravb_main.c | 27 ++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index ded87cb51650..03b127faf52f 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -2461,6 +2461,32 @@ static const struct ravb_hw_info ravb_gen2_hw_info = {
 	.magic_pkt = 1,
 };
 
+static const struct ravb_hw_info ravb_rzv2m_hw_info = {
+	.rx_ring_free = ravb_rx_ring_free_rcar,
+	.rx_ring_format = ravb_rx_ring_format_rcar,
+	.alloc_rx_desc = ravb_alloc_rx_desc_rcar,
+	.receive = ravb_rx_rcar,
+	.set_rate = ravb_set_rate_rcar,
+	.set_feature = ravb_set_features_rcar,
+	.dmac_init = ravb_dmac_init_rcar,
+	.emac_init = ravb_emac_init_rcar,
+	.gstrings_stats = ravb_gstrings_stats,
+	.gstrings_size = sizeof(ravb_gstrings_stats),
+	.net_hw_features = NETIF_F_RXCSUM,
+	.net_features = NETIF_F_RXCSUM,
+	.stats_len = ARRAY_SIZE(ravb_gstrings_stats),
+	.max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
+	.tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
+	.rx_max_buf_size = SZ_2K,
+	.multi_irqs = 1,
+	.err_mgmt_irqs = 1,
+	.gptp = 1,
+	.gptp_ptm_gic = 1,
+	.gptp_ref_clk = 1,
+	.nc_queues = 1,
+	.magic_pkt = 1,
+};
+
 static const struct ravb_hw_info gbeth_hw_info = {
 	.rx_ring_free = ravb_rx_ring_free_gbeth,
 	.rx_ring_format = ravb_rx_ring_format_gbeth,
@@ -2488,6 +2514,7 @@ static const struct of_device_id ravb_match_table[] = {
 	{ .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info },
 	{ .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info },
 	{ .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info },
+	{ .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info },
 	{ .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info },
 	{ }
 };
-- 
2.32.0

Re: [PATCH 4/9] ravb: Separate handling of irq enable/disable regs into feature

[Sergey Shtylyov]

On 5/4/22 5:54 PM, Phil Edworthy wrote:

> Currently, when the HW has a single interrupt, the driver uses the
> TIC, RIC0 registers to enable and disable RX/TX interrupts. When
> the HW has multiple interrupts, it uses the TIE, TID, RIE0, RID0
> registers.
> 
> However, other devices, e.g. RZ/V2M, have multiple irqs and use
> the TIC, RIC0 registers.

   s/use/have only/?

> Therefore, split this into a separate feature.
> 
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  drivers/net/ethernet/renesas/ravb.h      | 1 +
>  drivers/net/ethernet/renesas/ravb_main.c | 5 +++--
>  2 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
> index 15aa09d93ff0..67a240665cd2 100644
> --- a/drivers/net/ethernet/renesas/ravb.h
> +++ b/drivers/net/ethernet/renesas/ravb.h
> @@ -1027,6 +1027,7 @@ struct ravb_hw_info {
>  	unsigned tx_counters:1;		/* E-MAC has TX counters */
>  	unsigned carrier_counters:1;	/* E-MAC has carrier counters */
>  	unsigned multi_irqs:1;		/* AVB-DMAC and E-MAC has multiple irqs */
> +	unsigned irq_en_dis_regs:1;	/* Has separate irq enable and disable regs */

   Perhaps just irq_en_dis?

>  	unsigned gptp:1;		/* AVB-DMAC has gPTP support */
>  	unsigned ccc_gac:1;		/* AVB-DMAC has gPTP support active in config mode */
>  	unsigned gptp_ptm_gic:1;	/* gPTP enables Presentation Time Match irq via GIC */
[...]

MBR, Sergey

Re: [PATCH 3/9] ravb: Separate use of GIC reg for PTME from multi_irqs

[Sergey Shtylyov]

On 5/4/22 5:54 PM, Phil Edworthy wrote:

> When the HW has a single interrupt, the driver currently uses the
> PTME (Presentation Time Match Enable) bit in the GIC register to
> enable/disable the PTM irq. Otherwise, it uses the GIE/GID registers.
> 
> However, other SoCs, e.g. RZ/V2M, have multiple irqs and use the GIC
> register PTME bit, so separate it out as it's own feature.
> 
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  drivers/net/ethernet/renesas/ravb.h      | 1 +
>  drivers/net/ethernet/renesas/ravb_main.c | 1 +
>  drivers/net/ethernet/renesas/ravb_ptp.c  | 4 ++--
>  3 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
> index 08062d73df10..15aa09d93ff0 100644
> --- a/drivers/net/ethernet/renesas/ravb.h
> +++ b/drivers/net/ethernet/renesas/ravb.h
> @@ -1029,6 +1029,7 @@ struct ravb_hw_info {
>  	unsigned multi_irqs:1;		/* AVB-DMAC and E-MAC has multiple irqs */
>  	unsigned gptp:1;		/* AVB-DMAC has gPTP support */
>  	unsigned ccc_gac:1;		/* AVB-DMAC has gPTP support active in config mode */
> +	unsigned gptp_ptm_gic:1;	/* gPTP enables Presentation Time Match irq via GIC */

   I think this needs to be controlled by the 'irq_en_dis' feature bit from the patch #4.

[...]

MBR, Sergey

Re: [PATCH 0/9] Add Renesas RZ/V2M Ethernet support

[Jakub Kicinski]

On Wed,  4 May 2022 15:54:45 +0100 Phil Edworthy wrote:
> The RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB, though
> some small parts are the same as R-Car Gen2.
> Other differences are:
> * It has separate data (DI), error (Line 1) and management (Line 2) irqs
>   rather than one irq for all three.
> * Instead of using the High-speed peripheral bus clock for gPTP, it has
>   a separate gPTP reference clock.
> 
> The dts patches depend on v4 of the following patch set:
> "Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support"
> 
> Phil Edworthy (9):
>   clk: renesas: r9a09g011: Add eth clock and reset entries
>   dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC
>   ravb: Separate use of GIC reg for PTME from multi_irqs
>   ravb: Separate handling of irq enable/disable regs into feature
>   ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs
>   ravb: Use separate clock for gPTP
>   ravb: Add support for RZ/V2M
>   arm64: dts: renesas: r9a09g011: Add ethernet nodes
>   arm64: dts: renesas: rzv2m evk: Enable ethernet

How are you expecting this to be merged?

I think you should drop the first (clk) patch from this series 
so we can apply the series to net-next. And route the clk patch 
thru Geert's tree separately? 

Right now patchwork thinks the series is incomplete because it 
hasn't received patch 1.

Re: [PATCH 0/9] Add Renesas RZ/V2M Ethernet support

[Geert Uytterhoeven]

Hi Jakub,

On Thu, May 5, 2022 at 2:58 AM Jakub Kicinski <kuba@kernel.org> wrote:
> On Wed,  4 May 2022 15:54:45 +0100 Phil Edworthy wrote:
> > The RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB, though
> > some small parts are the same as R-Car Gen2.
> > Other differences are:
> > * It has separate data (DI), error (Line 1) and management (Line 2) irqs
> >   rather than one irq for all three.
> > * Instead of using the High-speed peripheral bus clock for gPTP, it has
> >   a separate gPTP reference clock.
> >
> > The dts patches depend on v4 of the following patch set:
> > "Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support"
> >
> > Phil Edworthy (9):
> >   clk: renesas: r9a09g011: Add eth clock and reset entries
> >   dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC
> >   ravb: Separate use of GIC reg for PTME from multi_irqs
> >   ravb: Separate handling of irq enable/disable regs into feature
> >   ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs
> >   ravb: Use separate clock for gPTP
> >   ravb: Add support for RZ/V2M
> >   arm64: dts: renesas: r9a09g011: Add ethernet nodes
> >   arm64: dts: renesas: rzv2m evk: Enable ethernet
>
> How are you expecting this to be merged?
>
> I think you should drop the first (clk) patch from this series
> so we can apply the series to net-next. And route the clk patch
> thru Geert's tree separately?

Same for the last two DTS patches, they should go through the
renesas-devel and SoC trees.

> Right now patchwork thinks the series is incomplete because it
> hasn't received patch 1.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 4/9] ravb: Separate handling of irq enable/disable regs into feature

[Phil Edworthy]

Hi Sergey,

On 04 May 2022 20:55 Sergey Shtylyov wrote:
> On 5/4/22 5:54 PM, Phil Edworthy wrote:
> 
> > Currently, when the HW has a single interrupt, the driver uses the
> > TIC, RIC0 registers to enable and disable RX/TX interrupts. When the
> > HW has multiple interrupts, it uses the TIE, TID, RIE0, RID0
> > registers.
> >
> > However, other devices, e.g. RZ/V2M, have multiple irqs and use the
> > TIC, RIC0 registers.
> 
>    s/use/have only/?
Yes, I'll fix that.
 
> > Therefore, split this into a separate feature.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >  drivers/net/ethernet/renesas/ravb.h      | 1 +
> >  drivers/net/ethernet/renesas/ravb_main.c | 5 +++--
> >  2 files changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/renesas/ravb.h
> > b/drivers/net/ethernet/renesas/ravb.h
> > index 15aa09d93ff0..67a240665cd2 100644
> > --- a/drivers/net/ethernet/renesas/ravb.h
> > +++ b/drivers/net/ethernet/renesas/ravb.h
> > @@ -1027,6 +1027,7 @@ struct ravb_hw_info {
> >  	unsigned tx_counters:1;		/* E-MAC has TX counters */
> >  	unsigned carrier_counters:1;	/* E-MAC has carrier counters */
> >  	unsigned multi_irqs:1;		/* AVB-DMAC and E-MAC has multiple
> irqs */
> > +	unsigned irq_en_dis_regs:1;	/* Has separate irq enable and disable
> regs */
> 
>    Perhaps just irq_en_dis?
Can do.

> >  	unsigned gptp:1;		/* AVB-DMAC has gPTP support */
> >  	unsigned ccc_gac:1;		/* AVB-DMAC has gPTP support active in
> config mode */
> >  	unsigned gptp_ptm_gic:1;	/* gPTP enables Presentation Time
> Match irq via GIC */
> [...]

Thanks
Phil

RE: [PATCH 3/9] ravb: Separate use of GIC reg for PTME from multi_irqs

[Phil Edworthy]

Hi Sergey,

On 04 May 2022 21:40 Sergey Shtylyov wrote:
> On 5/4/22 5:54 PM, Phil Edworthy wrote:
> 
> > When the HW has a single interrupt, the driver currently uses the
> > PTME (Presentation Time Match Enable) bit in the GIC register to
> > enable/disable the PTM irq. Otherwise, it uses the GIE/GID registers.
> >
> > However, other SoCs, e.g. RZ/V2M, have multiple irqs and use the GIC
> > register PTME bit, so separate it out as it's own feature.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >  drivers/net/ethernet/renesas/ravb.h      | 1 +
> >  drivers/net/ethernet/renesas/ravb_main.c | 1 +
> >  drivers/net/ethernet/renesas/ravb_ptp.c  | 4 ++--
> >  3 files changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/renesas/ravb.h
> b/drivers/net/ethernet/renesas/ravb.h
> > index 08062d73df10..15aa09d93ff0 100644
> > --- a/drivers/net/ethernet/renesas/ravb.h
> > +++ b/drivers/net/ethernet/renesas/ravb.h
> > @@ -1029,6 +1029,7 @@ struct ravb_hw_info {
> >  	unsigned multi_irqs:1;		/* AVB-DMAC and E-MAC has multiple
> irqs */
> >  	unsigned gptp:1;		/* AVB-DMAC has gPTP support */
> >  	unsigned ccc_gac:1;		/* AVB-DMAC has gPTP support active in
> config mode */
> > +	unsigned gptp_ptm_gic:1;	/* gPTP enables Presentation Time
> Match irq via GIC */
> 
>    I think this needs to be controlled by the 'irq_en_dis' feature bit
> from the patch #4.
Good point, I'll fix and squash the two patches.

Thanks
Phil

RE: [PATCH 0/9] Add Renesas RZ/V2M Ethernet support

[Phil Edworthy]

Hi Jakub, Geert,

On 05 May 2022 07:59 Geert Uytterhoeven wrote:
> On Thu, May 5, 2022 at 2:58 AM Jakub Kicinski wrote:
> > On Wed,  4 May 2022 15:54:45 +0100 Phil Edworthy wrote:
> > > The RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB,
> > > though some small parts are the same as R-Car Gen2.
> > > Other differences are:
> > > * It has separate data (DI), error (Line 1) and management (Line 2)
> irqs
> > >   rather than one irq for all three.
> > > * Instead of using the High-speed peripheral bus clock for gPTP, it
> has
> > >   a separate gPTP reference clock.
> > >
> > > The dts patches depend on v4 of the following patch set:
> > > "Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support"
> > >
> > > Phil Edworthy (9):
> > >   clk: renesas: r9a09g011: Add eth clock and reset entries
> > >   dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC
> > >   ravb: Separate use of GIC reg for PTME from multi_irqs
> > >   ravb: Separate handling of irq enable/disable regs into feature
> > >   ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt)
> irqs
> > >   ravb: Use separate clock for gPTP
> > >   ravb: Add support for RZ/V2M
> > >   arm64: dts: renesas: r9a09g011: Add ethernet nodes
> > >   arm64: dts: renesas: rzv2m evk: Enable ethernet
> >
> > How are you expecting this to be merged?
> >
> > I think you should drop the first (clk) patch from this series so we
> > can apply the series to net-next. And route the clk patch thru Geert's
> > tree separately?
> 
> Same for the last two DTS patches, they should go through the renesas-
> devel and SoC trees.
Sorry, I mistakenly assumed this was all going via Geert's tree, but of
course it's not. I'll split the series in two.


> > Right now patchwork thinks the series is incomplete because it hasn't
> > received patch 1.

Thanks
Phil

Re: [PATCH 6/9] ravb: Use separate clock for gPTP

[Sergey Shtylyov]

Hello!

On 5/4/22 5:54 PM, Phil Edworthy wrote:

> RZ/V2M has a separate gPTP reference clock that is used when the
> AVB-DMAC Mode Register (CCC) gPTP Clock Select (CSEL) bits are
> set to "01: High-speed peripheral bus clock".
> Therefore, add a feature that allows this clock to be used for
> gPTP.
> 
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru>

[...]
> diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
> index 73976a392457..f8706897ea41 100644
> --- a/drivers/net/ethernet/renesas/ravb.h
> +++ b/drivers/net/ethernet/renesas/ravb.h
> @@ -1032,6 +1032,7 @@ struct ravb_hw_info {
>  	unsigned gptp:1;		/* AVB-DMAC has gPTP support */
>  	unsigned ccc_gac:1;		/* AVB-DMAC has gPTP support active in config mode */
>  	unsigned gptp_ptm_gic:1;	/* gPTP enables Presentation Time Match irq via GIC */
> +	unsigned gptp_ref_clk:1;	/* gPTP has separate reference clock */

   Perhaps just gptp_clk?

[...]
> @@ -1043,6 +1044,7 @@ struct ravb_private {
>  	void __iomem *addr;
>  	struct clk *clk;
>  	struct clk *refclk;

   I wonder what that refclk feeds -- no word of it in the commit adding it...

> +	struct clk *gptp_clk;
>  	struct mdiobb_ctrl mdiobb;
>  	u32 num_rx_ring[NUM_RX_QUEUE];
>  	u32 num_tx_ring[NUM_TX_QUEUE];
[...]

MBR, Sergey

Re: [PATCH 5/9] ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs

[Sergey Shtylyov]

On 5/4/22 5:54 PM, Phil Edworthy wrote:

> R-Car has a combined interrupt line, ch22 = Line0_DiA | Line1_A | Line2_A.

   R-Car gen3, you mean? Because R-Car gen2 has single IRQ...

> RZ/V2M has separate interrupt lines for each of these, so add a feature
> that allows the driver to get these interrupts and call the common handler.
> 
> We keep the "ch22" name for Line0_DiA and "ch24" for Line3 interrupts to
> keep the code simple.

   Not sure I agree with such simplification -- at least about "ch22"...

> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

[...]
> diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
> index d0b9688074ca..f12a23b9c391 100644
> --- a/drivers/net/ethernet/renesas/ravb_main.c
> +++ b/drivers/net/ethernet/renesas/ravb_main.c
[...]
> @@ -2167,6 +2184,10 @@ static int ravb_close(struct net_device *ndev)
>  		free_irq(priv->rx_irqs[RAVB_BE], ndev);
>  		free_irq(priv->emac_irq, ndev);
>  	}
> +	if (info->err_mgmt_irqs) {
> +		free_irq(priv->erra_irq, ndev);
> +		free_irq(priv->mgmta_irq, ndev);
> +	}

   Shouldn't this be under:

	if (info->multi_irqs) {

above?

>  	free_irq(ndev->irq, ndev);
>  
>  	if (info->nc_queues)
> @@ -2665,6 +2686,22 @@ static int ravb_probe(struct platform_device *pdev)
>  		}
>  	}
>  
> +	if (info->err_mgmt_irqs) {
> +		irq = platform_get_irq_byname(pdev, "err_a");
> +		if (irq < 0) {
> +			error = irq;
> +			goto out_release;
> +		}
> +		priv->erra_irq = irq;
> +
> +		irq = platform_get_irq_byname(pdev, "mgmt_a");
> +		if (irq < 0) {
> +			error = irq;
> +			goto out_release;
> +		}
> +		priv->mgmta_irq = irq;
> +	}
> +

   Same here... 

>  	priv->clk = devm_clk_get(&pdev->dev, NULL);
>  	if (IS_ERR(priv->clk)) {
>  		error = PTR_ERR(priv->clk);

MBR, Sergey

Re: [PATCH 7/9] ravb: Add support for RZ/V2M

[Sergey Shtylyov]

On 5/4/22 5:54 PM, Phil Edworthy wrote:

> RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB, though
> some small parts are the same as R-Car Gen2.

   You mean the absence of the interrupt enable/disable registers?

> Other differences are:

   Differences to gen3, you mean?

> * It has separate data (DI), error (Line 1) and management (Line 2) irqs
>   rather than one irq for all three.
> * Instead of using the High-speed peripheral bus clock for gPTP, it has a
>   separate gPTP reference clock.
> 
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> Note: gPTP was tested using an RZ/V2M EVK and an R-Car M3N Salvator-XS
> board, connected with a Summit X440 AVB switch, using ptp4l.

   Oh, that's good! :-)

> ---
>  drivers/net/ethernet/renesas/ravb_main.c | 27 ++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
> index ded87cb51650..03b127faf52f 100644
> --- a/drivers/net/ethernet/renesas/ravb_main.c
> +++ b/drivers/net/ethernet/renesas/ravb_main.c
> @@ -2461,6 +2461,32 @@ static const struct ravb_hw_info ravb_gen2_hw_info = {
>  	.magic_pkt = 1,
>  };
>  
> +static const struct ravb_hw_info ravb_rzv2m_hw_info = {
> +	.rx_ring_free = ravb_rx_ring_free_rcar,
> +	.rx_ring_format = ravb_rx_ring_format_rcar,
> +	.alloc_rx_desc = ravb_alloc_rx_desc_rcar,
> +	.receive = ravb_rx_rcar,
> +	.set_rate = ravb_set_rate_rcar,
> +	.set_feature = ravb_set_features_rcar,
> +	.dmac_init = ravb_dmac_init_rcar,
> +	.emac_init = ravb_emac_init_rcar,
> +	.gstrings_stats = ravb_gstrings_stats,
> +	.gstrings_size = sizeof(ravb_gstrings_stats),
> +	.net_hw_features = NETIF_F_RXCSUM,
> +	.net_features = NETIF_F_RXCSUM,
> +	.stats_len = ARRAY_SIZE(ravb_gstrings_stats),
> +	.max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
> +	.tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
> +	.rx_max_buf_size = SZ_2K,

   What about .internal_delay and .tx_counters?

> +	.multi_irqs = 1,
> +	.err_mgmt_irqs = 1,
> +	.gptp = 1,

   Not .ccc_gac?

[...]

MBR. Sergey

Re: [PATCH 2/9] dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC

[Sergey Shtylyov]

Hello!

On 5/4/22 5:54 PM, Phil Edworthy wrote:

> Document the Ethernet AVB IP found on RZ/V2M SoC.
> It includes the Ethernet controller (E-MAC) and Dedicated Direct memory
> access controller (DMAC) for transferring transmitted Ethernet frames
> to and received Ethernet frames from respective storage areas in the
> URAM at high speed.

   I think nobody knows what exactly URAM stands for... you better call it
just RAM. :-)

> The AVB-DMAC is compliant with IEEE 802.1BA, IEEE 802.1AS timing and
> synchronization protocol, IEEE 802.1Qav real-time transfer, and the
> IEEE 802.1Qat stream reservation protocol.
> 
> R-Car has a pair of combined interrupt lines:
>  ch22 = Line0_DiA | Line1_A | Line2_A
>  ch23 = Line0_DiB | Line1_B | Line2_B
> Line0 for descriptor interrupts.
> Line1 for error related interrupts (which we call err_a and err_b).
> Line2 for management and gPTP related interrupts (mgmt_a and mgmt_b).
> 
> RZ/V2M hardware has separate interrupt lines for each of these, but
> we keep the "ch22" name for Line0_DiA.

   Not sure I agree here...
   BTW, aren't the interrupts called "Ethernet ABV.ch<n>" (as on R-Car gen3)
in your (complete?) manual?

> We also keep the "ch24" name for the Line3 (MAC) interrupt.
> 
> It has 3 clocks; the main AXI clock, the AMBA CHI clock and a gPTP

   Could you spell out CHI like below?

> reference clock.
> 
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
[...]

MBR, Sergey

RE: [PATCH 7/9] ravb: Add support for RZ/V2M

[Phil Edworthy]

Hi Sergey,

On 05 May 2022 21:18 Sergey Shtylyov wrote:
> On 5/4/22 5:54 PM, Phil Edworthy wrote:
> 
> > RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB, though
> > some small parts are the same as R-Car Gen2.
> 
>    You mean the absence of the interrupt enable/disable registers?
> 
> > Other differences are:
> 
>    Differences to gen3, you mean?
Differences to both gen3 and gen2.

 
> > * It has separate data (DI), error (Line 1) and management (Line 2) irqs
> >   rather than one irq for all three.
> > * Instead of using the High-speed peripheral bus clock for gPTP, it has
> a
> >   separate gPTP reference clock.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > Note: gPTP was tested using an RZ/V2M EVK and an R-Car M3N Salvator-XS
> > board, connected with a Summit X440 AVB switch, using ptp4l.
> 
>    Oh, that's good! :-)
btw, you should be able to test gPTP without an AVB switch if you connect
the boards directly. I haven't tried it as I'm using rootfs over NFS on
the rz/v2m board.

For ptp4l, I had to create a config file that increases tx_timestamp_timeout
on the rzv2m board:
  echo "[global]" > ptp.cfg
  echo "tx_timestamp_timeout    100" >> ptp.cfg
This increases the timeout waiting for the tx time stamp to 100ms, which is
excessive and it would likely work with 2ms. The default is 1ms.

Rcar gen3 didn’t need this config file, but it has a more powerful processor.
Though whilst familiarising myself with ptp4l I had some debug code in the
driver and that was enough for rcar to also need this config change.

Then just run ptp4l on both sides:
  ptp4l -i eth0 -m -f ./ptp.cfg


> > ---
> >  drivers/net/ethernet/renesas/ravb_main.c | 27 ++++++++++++++++++++++++
> >  1 file changed, 27 insertions(+)
> >
> > diff --git a/drivers/net/ethernet/renesas/ravb_main.c
> b/drivers/net/ethernet/renesas/ravb_main.c
> > index ded87cb51650..03b127faf52f 100644
> > --- a/drivers/net/ethernet/renesas/ravb_main.c
> > +++ b/drivers/net/ethernet/renesas/ravb_main.c
> > @@ -2461,6 +2461,32 @@ static const struct ravb_hw_info
> ravb_gen2_hw_info = {
> >  	.magic_pkt = 1,
> >  };
> >
> > +static const struct ravb_hw_info ravb_rzv2m_hw_info = {
> > +	.rx_ring_free = ravb_rx_ring_free_rcar,
> > +	.rx_ring_format = ravb_rx_ring_format_rcar,
> > +	.alloc_rx_desc = ravb_alloc_rx_desc_rcar,
> > +	.receive = ravb_rx_rcar,
> > +	.set_rate = ravb_set_rate_rcar,
> > +	.set_feature = ravb_set_features_rcar,
> > +	.dmac_init = ravb_dmac_init_rcar,
> > +	.emac_init = ravb_emac_init_rcar,
> > +	.gstrings_stats = ravb_gstrings_stats,
> > +	.gstrings_size = sizeof(ravb_gstrings_stats),
> > +	.net_hw_features = NETIF_F_RXCSUM,
> > +	.net_features = NETIF_F_RXCSUM,
> > +	.stats_len = ARRAY_SIZE(ravb_gstrings_stats),
> > +	.max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
> > +	.tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
> > +	.rx_max_buf_size = SZ_2K,
> 
>    What about .internal_delay and .tx_counters?
rz/v2m doesn't have the APSR reg, so .internal_delay = 0, and doesn't
have the TROCR reg, so .tx_counters = 0


> > +	.multi_irqs = 1,
> > +	.err_mgmt_irqs = 1,
> > +	.gptp = 1,
> 
>    Not .ccc_gac?
Nope, not on this device.

Thanks
Phil

RE: [PATCH 5/9] ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs

[Phil Edworthy]

Hi Sergey,

On 05 May 2022 20:41 Sergey Shtylyov wrote:
> On 5/4/22 5:54 PM, Phil Edworthy wrote:
> 
> > R-Car has a combined interrupt line, ch22 = Line0_DiA | Line1_A |
> Line2_A.
> 
>    R-Car gen3, you mean? Because R-Car gen2 has single IRQ...
> 
> > RZ/V2M has separate interrupt lines for each of these, so add a
> > feature that allows the driver to get these interrupts and call the
> common handler.
> >
> > We keep the "ch22" name for Line0_DiA and "ch24" for Line3 interrupts
> > to keep the code simple.
> 
>    Not sure I agree with such simplification -- at least about "ch22"...
Ok, I can change it.


> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> [...]
> > diff --git a/drivers/net/ethernet/renesas/ravb_main.c
> > b/drivers/net/ethernet/renesas/ravb_main.c
> > index d0b9688074ca..f12a23b9c391 100644
> > --- a/drivers/net/ethernet/renesas/ravb_main.c
> > +++ b/drivers/net/ethernet/renesas/ravb_main.c
> [...]
> > @@ -2167,6 +2184,10 @@ static int ravb_close(struct net_device *ndev)
> >  		free_irq(priv->rx_irqs[RAVB_BE], ndev);
> >  		free_irq(priv->emac_irq, ndev);
> >  	}
> > +	if (info->err_mgmt_irqs) {
> > +		free_irq(priv->erra_irq, ndev);
> > +		free_irq(priv->mgmta_irq, ndev);
> > +	}
> 
>    Shouldn't this be under:
> 
> 	if (info->multi_irqs) {
> 
> above?
Can do, though I guess we could also have devices in the future that
have separate err and mgmt interrupts, but not use the multiple channel
interrupts.
I'm easy either way.

> >  	free_irq(ndev->irq, ndev);
> >
> >  	if (info->nc_queues)
> > @@ -2665,6 +2686,22 @@ static int ravb_probe(struct platform_device
> *pdev)
> >  		}
> >  	}
> >
> > +	if (info->err_mgmt_irqs) {
> > +		irq = platform_get_irq_byname(pdev, "err_a");
> > +		if (irq < 0) {
> > +			error = irq;
> > +			goto out_release;
> > +		}
> > +		priv->erra_irq = irq;
> > +
> > +		irq = platform_get_irq_byname(pdev, "mgmt_a");
> > +		if (irq < 0) {
> > +			error = irq;
> > +			goto out_release;
> > +		}
> > +		priv->mgmta_irq = irq;
> > +	}
> > +
> 
>    Same here...
> 
> >  	priv->clk = devm_clk_get(&pdev->dev, NULL);
> >  	if (IS_ERR(priv->clk)) {
> >  		error = PTR_ERR(priv->clk);


Thanks
Phil

RE: [PATCH 2/9] dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC

[Phil Edworthy]

Hi Sergey,

On 07 May 2022 19:21 Sergey Shtylyov wrote:
> On 5/4/22 5:54 PM, Phil Edworthy wrote:
> 
> > Document the Ethernet AVB IP found on RZ/V2M SoC.
> > It includes the Ethernet controller (E-MAC) and Dedicated Direct memory
> > access controller (DMAC) for transferring transmitted Ethernet frames
> > to and received Ethernet frames from respective storage areas in the
> > URAM at high speed.
> 
>    I think nobody knows what exactly URAM stands for... you better call it
> just RAM. :-)
Going point!

 
> > The AVB-DMAC is compliant with IEEE 802.1BA, IEEE 802.1AS timing and
> > synchronization protocol, IEEE 802.1Qav real-time transfer, and the
> > IEEE 802.1Qat stream reservation protocol.
> >
> > R-Car has a pair of combined interrupt lines:
> >  ch22 = Line0_DiA | Line1_A | Line2_A
> >  ch23 = Line0_DiB | Line1_B | Line2_B
> > Line0 for descriptor interrupts.
> > Line1 for error related interrupts (which we call err_a and err_b).
> > Line2 for management and gPTP related interrupts (mgmt_a and mgmt_b).
> >
> > RZ/V2M hardware has separate interrupt lines for each of these, but
> > we keep the "ch22" name for Line0_DiA.
> 
>    Not sure I agree here...
Ok, I'll use "dia" instead of ch22, and "line3" instead of ch24 on rz/v2m.
Is that ok?


>    BTW, aren't the interrupts called "Ethernet ABV.ch<n>" (as on R-Car
> gen3)
> in your (complete?) manual?
No, they are:
pif_intr_line_0_rx_n[0..17] for Line0_Rx[0..17] 
pif_intr_line_0_tx_n[0..3]  for Line0_Tx[0..3]
pif_intr_line_0_dia_n       for Line0_DiA
pif_intr_line_0_dib_n       for Line0_DiB
pif_intr_line_1_a_n         for Line1_A
pif_intr_line_1_b_n         for Line1_B
pif_intr_line_2_a_n         for Line2_A
pif_intr_line_2_b_n         for Line2_B
pif_intr_line_3_n           for Line3

The full HW manual is available, but an NDA is required:
https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output#document
"[NDA Required] RZ/V2M User's Manual: Hardware (Additional document)"


> > We also keep the "ch24" name for the Line3 (MAC) interrupt.
> >
> > It has 3 clocks; the main AXI clock, the AMBA CHI clock and a gPTP
> 
>    Could you spell out CHI like below?
Will do.


> > reference clock.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> [...]

Thanks
Phil