From: Andrew Lunn <andrew@lunn.ch>
To: Dario Alcocer <dalcocer@helixd.com>
Cc: netdev@vger.kernel.org
Subject: Re: Marvell switch port shows LOWERLAYERDOWN, ping fails
Date: Fri, 23 Jul 2021 20:25:32 +0200 [thread overview]
Message-ID: <YPsJnLCKVzEUV5cb@lunn.ch> (raw)
In-Reply-To: <0188e53d-1535-658a-4134-a5f05f214bef@helixd.com>
> > You probably don't want both ends of the link in rgmii-id mode. That
> > will give you twice the delay.
>
> Ok, I'll change phy-mode to "rgmii" for both ends. It's a little confusing
> that there's a reference to phy-mode at all, though, given the actual
> connection is SERDES. My understanding is SERDES is a digital, PHY-less
> connection.
Is it even RGMII? You say SERDES, so 1000BaseX seems more likely.
Andrew
next prev parent reply other threads:[~2021-07-23 18:25 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-22 22:55 Marvell switch port shows LOWERLAYERDOWN, ping fails Dario Alcocer
2021-07-23 13:41 ` Andrew Lunn
2021-07-23 18:21 ` Dario Alcocer
2021-07-23 18:25 ` Andrew Lunn [this message]
2021-07-23 18:36 ` Dario Alcocer
2021-07-23 21:58 ` Dario Alcocer
2021-07-24 17:34 ` Andrew Lunn
2021-07-25 2:26 ` Dario Alcocer
2021-07-25 2:36 ` Dario Alcocer
2021-07-27 1:39 ` Dario Alcocer
2021-07-28 18:07 ` Dario Alcocer
2021-07-28 18:23 ` Andrew Lunn
2021-07-28 18:33 ` Dario Alcocer
2021-07-28 19:24 ` Andrew Lunn
2021-07-28 19:37 ` Dario Alcocer
2021-07-28 20:47 ` Andrew Lunn
2021-07-28 20:54 ` Dario Alcocer
2021-07-28 21:09 ` Andrew Lunn
2021-08-05 21:44 ` Dario Alcocer
2021-08-06 16:03 ` Dario Alcocer
2021-08-06 23:46 ` Dario Alcocer
2021-08-07 18:57 ` Andrew Lunn
2021-08-09 16:28 ` Dario Alcocer
2021-08-10 20:58 ` Dario Alcocer
2021-08-10 22:13 ` Andrew Lunn
2021-08-11 13:16 ` Dario Alcocer
2021-08-07 17:44 ` Andrew Lunn
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