Re: Marvell switch port shows LOWERLAYERDOWN, ping fails

[Andrew Lunn <andrew@lunn.ch>]

On Tue, Aug 10, 2021 at 01:58:21PM -0700, Dario Alcocer wrote:
> Well, I misread the schematic; the DSA ports are connected via four pins on
> each of the MV88E6176 chips (S_RXP, S_RXN, S_TXP, S_TXN):
> 
> S_RXP (PHY 0x1E) <---> S_TXP (PHY 0x1A)
> S_RXN (PHY 0x1E) <---> S_TXN (PHY 0x1A)
> S_TXP (PHY 0x1E) <---> S_RXP (PHY 0x1A)
> S_TXN (PHY 0x1E) <---> S_RXN (PHY 0x1A)
> 
> As you mentioned before, 1G requires 4 pairs. Thus, it seems that phy-mode =
> "1000base-x" and speed = <1000> cannot be used for the SERDES link.

You are mixing up the link from a MAC to a PHY, and from a PHY over a
cable to another PHY.

An Ethernet cable has 4 pairs, and it is the PHYs job to generate and
receive the signals over these four pairs. How those signals look is
all part of the 802.3 standard, nothing you can configure.

There are a number of different ways you can connect a MAC to a PHY,
or a MAC to another MAC. The generic name for this is MII, Media
Independent Interface.  The number of copper tracks between the MAC
and PHY varies. Gigabit MII has around 22 pins, here as Reduced
Gigabit MII has 11 pins. And a SERDES 100Base-X only has 4 pins.

So 1000base-x is correct.

I don't have the datasheet for the 6176, but i assume it is similar to
the 6352. The SERDES can be connected to either port4 or port5. The
S_SEL pin is used to configure this. For the 6352, S_SEL=1 means port
5. You can also configure the port to 100Base-FX or 1000Base-X/SGMII
using the S_MODE pin. S_MODE=1 means 1000Base-X or SGMII.

The CMODE, or Config mode, the lowest nibble of the port status
register, tells you what it is actually using. A value of 0xf means a
copper PHY. 0x8 is 100Base-FX. 0x9 = 1000Base-X, 0x0a = SGMII.

       Andrew