From: Andrew Lunn <andrew@lunn.ch>
To: Dario Alcocer <dalcocer@helixd.com>
Cc: netdev@vger.kernel.org
Subject: Re: Marvell switch port shows LOWERLAYERDOWN, ping fails
Date: Wed, 28 Jul 2021 20:23:58 +0200 [thread overview]
Message-ID: <YQGgvj2e7dqrHDCc@lunn.ch> (raw)
In-Reply-To: <fb7ced72-384c-9908-0a35-5f425ec52748@helixd.com>
On Wed, Jul 28, 2021 at 11:07:37AM -0700, Dario Alcocer wrote:
> It appears the port link-state issue is caused by the mv88e6xxx switch
> driver. The function mv88e6xxx_mac_config identifies the PHY as internal and
> skips the call to mv88e6xxx_port_setup_mac.
>
> It does not make sense to me why internal PHY configuration should be
> skipped.
The switch should do the configuration itself for internal PHYs. At
least that works for other switches. What value does CMODE have for
the port? 0xf?
Andrew
next prev parent reply other threads:[~2021-07-28 18:24 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-22 22:55 Marvell switch port shows LOWERLAYERDOWN, ping fails Dario Alcocer
2021-07-23 13:41 ` Andrew Lunn
2021-07-23 18:21 ` Dario Alcocer
2021-07-23 18:25 ` Andrew Lunn
2021-07-23 18:36 ` Dario Alcocer
2021-07-23 21:58 ` Dario Alcocer
2021-07-24 17:34 ` Andrew Lunn
2021-07-25 2:26 ` Dario Alcocer
2021-07-25 2:36 ` Dario Alcocer
2021-07-27 1:39 ` Dario Alcocer
2021-07-28 18:07 ` Dario Alcocer
2021-07-28 18:23 ` Andrew Lunn [this message]
2021-07-28 18:33 ` Dario Alcocer
2021-07-28 19:24 ` Andrew Lunn
2021-07-28 19:37 ` Dario Alcocer
2021-07-28 20:47 ` Andrew Lunn
2021-07-28 20:54 ` Dario Alcocer
2021-07-28 21:09 ` Andrew Lunn
2021-08-05 21:44 ` Dario Alcocer
2021-08-06 16:03 ` Dario Alcocer
2021-08-06 23:46 ` Dario Alcocer
2021-08-07 18:57 ` Andrew Lunn
2021-08-09 16:28 ` Dario Alcocer
2021-08-10 20:58 ` Dario Alcocer
2021-08-10 22:13 ` Andrew Lunn
2021-08-11 13:16 ` Dario Alcocer
2021-08-07 17:44 ` Andrew Lunn
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