Re: [PATCH] phy: mediatek: rework the floating point comparisons to fixed point

[kernel test robot <lkp@intel.com>]

Hi Tom,

kernel test robot noticed the following build warnings:

[auto build test WARNING on next-20230428]
[cannot apply to linus/master pza/reset/next pza/imx-drm/next mbgg-mediatek/for-next v6.3 v6.3-rc7 v6.3-rc6 v6.3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Tom-Rix/phy-mediatek-rework-the-floating-point-comparisons-to-fixed-point/20230501-110044
base:   next-20230428
patch link:    https://lore.kernel.org/r/20230501025716.2905609-1-trix%40redhat.com
patch subject: [PATCH] phy: mediatek: rework the floating point comparisons to fixed point
config: arm64-randconfig-r026-20230430 (https://download.01.org/0day-ci/archive/20230501/202305011302.fwiJuq8v-lkp@intel.com/config)
compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project b1465cd49efcbc114a75220b153f5a055ce7911f)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm64 cross compiling tool for clang build
        # apt-get install binutils-aarch64-linux-gnu
        # https://github.com/intel-lab-lkp/linux/commit/7a707b74a3a3ce9d018ee340e478e5c75301c894
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Tom-Rix/phy-mediatek-rework-the-floating-point-comparisons-to-fixed-point/20230501-110044
        git checkout 7a707b74a3a3ce9d018ee340e478e5c75301c894
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/phy/mediatek/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202305011302.fwiJuq8v-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:298:6: warning: variable 'ret' is uninitialized when used here [-Wuninitialized]
           if (ret)
               ^~~
   drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:216:12: note: initialize the variable 'ret' to silence this warning
           int i, ret;
                     ^
                      = 0
>> drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:331:32: warning: result of comparison of constant 74175000000 with expression of type 'u32' (aka 'unsigned int') is always false [-Wtautological-constant-out-of-range-compare]
           } else if ((pixel_clk * 1000) >= 74175 * MEGA && pixel_clk <= 300 * MEGA) {
                      ~~~~~~~~~~~~~~~~~~ ^  ~~~~~~~~~~~~
>> drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:336:58: warning: result of comparison of constant 74175000000 with expression of type 'u32' (aka 'unsigned int') is always true [-Wtautological-constant-out-of-range-compare]
           } else if (pixel_clk >= 27 * MEGA && (pixel_clk * 1000) < 74175 * MEGA) {
                                                ~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~
   3 warnings generated.


vim +331 drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

   303	
   304	static int mtk_hdmi_pll_drv_setting(struct clk_hw *hw)
   305	{
   306		struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
   307		void __iomem *regs = hdmi_phy->regs;
   308		u8 data_channel_bias, clk_channel_bias;
   309		u8 impedance, impedance_en;
   310		u32 tmds_clk;
   311		u32 pixel_clk = hdmi_phy->pll_rate;
   312	
   313		tmds_clk = pixel_clk;
   314	
   315		/* bias & impedance setting:
   316		 * 3G < data rate <= 6G: enable impedance 100ohm,
   317		 *      data channel bias 24mA, clock channel bias 20mA
   318		 * pixel clk >= HD,  74.175MHZ <= pixel clk <= 300MHZ:
   319		 *      enalbe impedance 100ohm
   320		 *      data channel 20mA, clock channel 16mA
   321		 * 27M =< pixel clk < 74.175: disable impedance
   322		 *      data channel & clock channel bias 10mA
   323		 */
   324	
   325		/* 3G < data rate <= 6G, 300M < tmds rate <= 594M */
   326		if (tmds_clk > 300 * MEGA && tmds_clk <= 594 * MEGA) {
   327			data_channel_bias = 0x3c; /* 24mA */
   328			clk_channel_bias = 0x34; /* 20mA */
   329			impedance_en = 0xf;
   330			impedance = 0x36; /* 100ohm */
 > 331		} else if ((pixel_clk * 1000) >= 74175 * MEGA && pixel_clk <= 300 * MEGA) {
   332			data_channel_bias = 0x34; /* 20mA */
   333			clk_channel_bias = 0x2c; /* 16mA */
   334			impedance_en = 0xf;
   335			impedance = 0x36; /* 100ohm */
 > 336		} else if (pixel_clk >= 27 * MEGA && (pixel_clk * 1000) < 74175 * MEGA) {
   337			data_channel_bias = 0x14; /* 10mA */
   338			clk_channel_bias = 0x14; /* 10mA */
   339			impedance_en = 0x0;
   340			impedance = 0x0;
   341		} else {
   342			return -EINVAL;
   343		}
   344	
   345		/* bias */
   346		mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D0, data_channel_bias);
   347		mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D1, data_channel_bias);
   348		mtk_phy_update_field(regs + HDMI_1_CFG_1, RG_HDMITX21_DRV_IBIAS_D2, data_channel_bias);
   349		mtk_phy_update_field(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_IBIAS_CLK, clk_channel_bias);
   350	
   351		/* impedance */
   352		mtk_phy_update_field(regs + HDMI_1_CFG_0, RG_HDMITX21_DRV_IMP_EN, impedance_en);
   353		mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D0_EN1, impedance);
   354		mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D1_EN1, impedance);
   355		mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_D2_EN1, impedance);
   356		mtk_phy_update_field(regs + HDMI_1_CFG_2, RG_HDMITX21_DRV_IMP_CLK_EN1, impedance);
   357	
   358		return 0;
   359	}
   360	

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