From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v2 02/10] target/arm: Implement v8.1M NOCP handling
Date: Mon, 19 Oct 2020 09:11:41 -0700 [thread overview]
Message-ID: <037b3fbf-45e3-eec6-dcf3-76344405b8f6@linaro.org> (raw)
In-Reply-To: <20201019151301.2046-3-peter.maydell@linaro.org>
On 10/19/20 8:12 AM, Peter Maydell wrote:
> From v8.1M, disabled-coprocessor handling changes slightly:
> * coprocessors 8, 9, 14 and 15 are also governed by the
> cp10 enable bit, like cp11
> * an extra range of instruction patterns is considered
> to be inside the coprocessor space
>
> We previously marked these up with TODO comments; implement the
> correct behaviour.
>
> Unfortunately there is no ID register field which indicates this
> behaviour. We could in theory test an unrelated ID register which
> indicates guaranteed-to-be-in-v8.1M behaviour like ID_ISAR0.CmpBranch
>> = 3 (low-overhead-loops), but it seems better to simply define a new
> ARM_FEATURE_V8_1M feature flag and use it for this and other
> new-in-v8.1M behaviour that isn't identifiable from the ID registers.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/cpu.h | 1 +
> target/arm/m-nocp.decode | 10 ++++++----
> target/arm/translate-vfp.c.inc | 17 +++++++++++++++--
> 3 files changed, 22 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2020-10-19 16:13 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-19 15:12 [PATCH v2 00/10] target/arm: Various v8.1M minor features Peter Maydell
2020-10-19 15:12 ` [PATCH v2 01/10] decodetree: Fix codegen for non-overlapping group inside overlapping group Peter Maydell
2020-10-19 15:12 ` [PATCH v2 02/10] target/arm: Implement v8.1M NOCP handling Peter Maydell
2020-10-19 16:11 ` Richard Henderson [this message]
2020-10-19 15:12 ` [PATCH v2 03/10] target/arm: Implement v8.1M conditional-select insns Peter Maydell
2020-10-19 15:12 ` [PATCH v2 04/10] target/arm: Make the t32 insn[25:23]=111 group non-overlapping Peter Maydell
2020-10-19 15:12 ` [PATCH v2 05/10] target/arm: Don't allow BLX imm for M-profile Peter Maydell
2020-10-19 15:12 ` [PATCH v2 06/10] target/arm: Implement v8.1M branch-future insns (as NOPs) Peter Maydell
2020-10-19 15:12 ` [PATCH v2 07/10] target/arm: Implement v8.1M low-overhead-loop instructions Peter Maydell
2020-10-19 15:39 ` Richard Henderson
2020-10-19 15:12 ` [PATCH v2 08/10] target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile Peter Maydell
2020-10-19 15:13 ` [PATCH v2 09/10] target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16 Peter Maydell
2020-10-19 15:57 ` Richard Henderson
2020-10-19 15:13 ` [PATCH v2 10/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension Peter Maydell
2020-10-19 16:00 ` Richard Henderson
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