From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v2 08/10] target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile
Date: Mon, 19 Oct 2020 16:12:59 +0100 [thread overview]
Message-ID: <20201019151301.2046-9-peter.maydell@linaro.org> (raw)
In-Reply-To: <20201019151301.2046-1-peter.maydell@linaro.org>
In arm_cpu_realizefn(), if the CPU has VFP or Neon disabled then we
squash the ID register fields so that we don't advertise it to the
guest. This code was written for A-profile and needs some tweaks to
work correctly on M-profile:
* A-profile only fields should not be zeroed on M-profile:
- MVFR0.FPSHVEC,FPTRAP
- MVFR1.SIMDLS,SIMDINT,SIMDSP,SIMDHP
- MVFR2.SIMDMISC
* M-profile only fields should be zeroed on M-profile:
- MVFR1.FP16
In particular, because MVFR1.SIMDHP on A-profile is the same field as
MVFR1.FP16 on M-profile this code was incorrectly disabling FP16
support on an M-profile CPU (where has_neon is always false). This
isn't a visible bug yet because we don't have any M-profile CPUs with
FP16 support, but the change is necessary before we introduce any.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 29 ++++++++++++++++++-----------
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 056319859fb..186ee621a65 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1429,17 +1429,22 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
u = cpu->isar.mvfr0;
u = FIELD_DP32(u, MVFR0, FPSP, 0);
u = FIELD_DP32(u, MVFR0, FPDP, 0);
- u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0);
u = FIELD_DP32(u, MVFR0, FPSQRT, 0);
- u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
u = FIELD_DP32(u, MVFR0, FPROUND, 0);
+ if (!arm_feature(env, ARM_FEATURE_M)) {
+ u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
+ u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
+ }
cpu->isar.mvfr0 = u;
u = cpu->isar.mvfr1;
u = FIELD_DP32(u, MVFR1, FPFTZ, 0);
u = FIELD_DP32(u, MVFR1, FPDNAN, 0);
u = FIELD_DP32(u, MVFR1, FPHP, 0);
+ if (arm_feature(env, ARM_FEATURE_M)) {
+ u = FIELD_DP32(u, MVFR1, FP16, 0);
+ }
cpu->isar.mvfr1 = u;
u = cpu->isar.mvfr2;
@@ -1475,16 +1480,18 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
cpu->isar.id_isar6 = u;
- u = cpu->isar.mvfr1;
- u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
- u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
- u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
- u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
- cpu->isar.mvfr1 = u;
+ if (!arm_feature(env, ARM_FEATURE_M)) {
+ u = cpu->isar.mvfr1;
+ u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
+ u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
+ u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
+ u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
+ cpu->isar.mvfr1 = u;
- u = cpu->isar.mvfr2;
- u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
- cpu->isar.mvfr2 = u;
+ u = cpu->isar.mvfr2;
+ u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
+ cpu->isar.mvfr2 = u;
+ }
}
if (!cpu->has_neon && !cpu->has_vfp) {
--
2.20.1
next prev parent reply other threads:[~2020-10-19 15:27 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-19 15:12 [PATCH v2 00/10] target/arm: Various v8.1M minor features Peter Maydell
2020-10-19 15:12 ` [PATCH v2 01/10] decodetree: Fix codegen for non-overlapping group inside overlapping group Peter Maydell
2020-10-19 15:12 ` [PATCH v2 02/10] target/arm: Implement v8.1M NOCP handling Peter Maydell
2020-10-19 16:11 ` Richard Henderson
2020-10-19 15:12 ` [PATCH v2 03/10] target/arm: Implement v8.1M conditional-select insns Peter Maydell
2020-10-19 15:12 ` [PATCH v2 04/10] target/arm: Make the t32 insn[25:23]=111 group non-overlapping Peter Maydell
2020-10-19 15:12 ` [PATCH v2 05/10] target/arm: Don't allow BLX imm for M-profile Peter Maydell
2020-10-19 15:12 ` [PATCH v2 06/10] target/arm: Implement v8.1M branch-future insns (as NOPs) Peter Maydell
2020-10-19 15:12 ` [PATCH v2 07/10] target/arm: Implement v8.1M low-overhead-loop instructions Peter Maydell
2020-10-19 15:39 ` Richard Henderson
2020-10-19 15:12 ` Peter Maydell [this message]
2020-10-19 15:13 ` [PATCH v2 09/10] target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16 Peter Maydell
2020-10-19 15:57 ` Richard Henderson
2020-10-19 15:13 ` [PATCH v2 10/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension Peter Maydell
2020-10-19 16:00 ` Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20201019151301.2046-9-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).