[PATCH v2 00/10] target/arm: Various v8.1M minor features

[Peter Maydell <peter.maydell@linaro.org>]

This patchseries implements various minor v8.1M new features,
notably the branch-future and low-overhead-loop extensions.

(None of this will get enabled until we have enough to implement
a CPU model which has v8.1M, which will be the Cortex-M55, but
as usual we can get stuff into the tree gradually.)

Changes v1->v2:
 * added missing check that rm!=13 for CSEL decode
 * folded in gen_jmp_tb() fixup for DLS/WLS/LE patch
 * reversed sense of branch in trans_WLS
 * reworked set_fpscr changes as suggested by RTH
 * provide an env->v7m.ltpsize now (always 4 until
   MVE implemented, but it avoids code changes later)

Unreviewed patches: 2, 7, 9, 10

thanks
-- PMM

Peter Maydell (10):
  decodetree: Fix codegen for non-overlapping group inside overlapping
    group
  target/arm: Implement v8.1M NOCP handling
  target/arm: Implement v8.1M conditional-select insns
  target/arm: Make the t32 insn[25:23]=111 group non-overlapping
  target/arm: Don't allow BLX imm for M-profile
  target/arm: Implement v8.1M branch-future insns (as NOPs)
  target/arm: Implement v8.1M low-overhead-loop instructions
  target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile
  target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16
  target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension

 target/arm/cpu.h               |   8 ++
 target/arm/m-nocp.decode       |  10 +-
 target/arm/t32.decode          |  50 ++++++---
 target/arm/cpu.c               |  38 +++++--
 target/arm/translate.c         | 181 ++++++++++++++++++++++++++++++++-
 target/arm/vfp_helper.c        |  53 ++++++----
 scripts/decodetree.py          |   2 +-
 target/arm/translate-vfp.c.inc |  17 +++-
 8 files changed, 305 insertions(+), 54 deletions(-)

-- 
2.20.1