Re: [PATCH v2 10/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension

[Richard Henderson <richard.henderson@linaro.org>]

On 10/19/20 8:13 AM, Peter Maydell wrote:
> If the M-profile low-overhead-branch extension is implemented, FPSCR
> bits [18:16] are a new field LTPSIZE.  If MVE is not implemented
> (currently always true for us) then this field always reads as 4 and
> ignores writes.
> 
> These bits used to be the vector-length field for the old
> short-vector extension, so we need to take care that they are not
> misinterpreted as setting vec_len. We do this with a rearrangement
> of the vfp_set_fpscr() code that deals with vec_len, vec_stride
> and also the QC bit; this obviates the need for the M-profile
> only masking step that we used to have at the start of the function.
> 
> We provide a new field in CPUState for LTPSIZE, even though this
> will always be 4, in preparation for MVE, so we don't have to
> come back later and split it out of the vfp.xregs[FPSCR] value.
> (This state struct field will be saved and restored as part of
> the FPSCR value via the vmstate_fpscr in machine.c.)
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target/arm/cpu.h        | 1 +
>  target/arm/cpu.c        | 9 +++++++++
>  target/arm/vfp_helper.c | 6 ++++++
>  3 files changed, 16 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~