From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 31/49] target/arm: Implement pauth_computepac
Date: Fri, 18 Jan 2019 14:57:47 +0000 [thread overview]
Message-ID: <20190118145805.6852-32-peter.maydell@linaro.org> (raw)
In-Reply-To: <20190118145805.6852-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
This is the main crypto routine, an implementation of QARMA.
This matches, as much as possible, ARM pseudocode.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20190108223129.5570-28-richard.henderson@linaro.org
[PMM: fixed minor checkpatch nits]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/pauth_helper.c | 242 +++++++++++++++++++++++++++++++++++++-
1 file changed, 241 insertions(+), 1 deletion(-)
diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
index bc89dd8c111..d750f96edf0 100644
--- a/target/arm/pauth_helper.c
+++ b/target/arm/pauth_helper.c
@@ -26,10 +26,250 @@
#include "tcg/tcg-gvec-desc.h"
+static uint64_t pac_cell_shuffle(uint64_t i)
+{
+ uint64_t o = 0;
+
+ o |= extract64(i, 52, 4);
+ o |= extract64(i, 24, 4) << 4;
+ o |= extract64(i, 44, 4) << 8;
+ o |= extract64(i, 0, 4) << 12;
+
+ o |= extract64(i, 28, 4) << 16;
+ o |= extract64(i, 48, 4) << 20;
+ o |= extract64(i, 4, 4) << 24;
+ o |= extract64(i, 40, 4) << 28;
+
+ o |= extract64(i, 32, 4) << 32;
+ o |= extract64(i, 12, 4) << 36;
+ o |= extract64(i, 56, 4) << 40;
+ o |= extract64(i, 20, 4) << 44;
+
+ o |= extract64(i, 8, 4) << 48;
+ o |= extract64(i, 36, 4) << 52;
+ o |= extract64(i, 16, 4) << 56;
+ o |= extract64(i, 60, 4) << 60;
+
+ return o;
+}
+
+static uint64_t pac_cell_inv_shuffle(uint64_t i)
+{
+ uint64_t o = 0;
+
+ o |= extract64(i, 12, 4);
+ o |= extract64(i, 24, 4) << 4;
+ o |= extract64(i, 48, 4) << 8;
+ o |= extract64(i, 36, 4) << 12;
+
+ o |= extract64(i, 56, 4) << 16;
+ o |= extract64(i, 44, 4) << 20;
+ o |= extract64(i, 4, 4) << 24;
+ o |= extract64(i, 16, 4) << 28;
+
+ o |= i & MAKE_64BIT_MASK(32, 4);
+ o |= extract64(i, 52, 4) << 36;
+ o |= extract64(i, 28, 4) << 40;
+ o |= extract64(i, 8, 4) << 44;
+
+ o |= extract64(i, 20, 4) << 48;
+ o |= extract64(i, 0, 4) << 52;
+ o |= extract64(i, 40, 4) << 56;
+ o |= i & MAKE_64BIT_MASK(60, 4);
+
+ return o;
+}
+
+static uint64_t pac_sub(uint64_t i)
+{
+ static const uint8_t sub[16] = {
+ 0xb, 0x6, 0x8, 0xf, 0xc, 0x0, 0x9, 0xe,
+ 0x3, 0x7, 0x4, 0x5, 0xd, 0x2, 0x1, 0xa,
+ };
+ uint64_t o = 0;
+ int b;
+
+ for (b = 0; b < 64; b += 16) {
+ o |= (uint64_t)sub[(i >> b) & 0xf] << b;
+ }
+ return o;
+}
+
+static uint64_t pac_inv_sub(uint64_t i)
+{
+ static const uint8_t inv_sub[16] = {
+ 0x5, 0xe, 0xd, 0x8, 0xa, 0xb, 0x1, 0x9,
+ 0x2, 0x6, 0xf, 0x0, 0x4, 0xc, 0x7, 0x3,
+ };
+ uint64_t o = 0;
+ int b;
+
+ for (b = 0; b < 64; b += 16) {
+ o |= (uint64_t)inv_sub[(i >> b) & 0xf] << b;
+ }
+ return o;
+}
+
+static int rot_cell(int cell, int n)
+{
+ /* 4-bit rotate left by n. */
+ cell |= cell << 4;
+ return extract32(cell, 4 - n, 4);
+}
+
+static uint64_t pac_mult(uint64_t i)
+{
+ uint64_t o = 0;
+ int b;
+
+ for (b = 0; b < 4 * 4; b += 4) {
+ int i0, i4, i8, ic, t0, t1, t2, t3;
+
+ i0 = extract64(i, b, 4);
+ i4 = extract64(i, b + 4 * 4, 4);
+ i8 = extract64(i, b + 8 * 4, 4);
+ ic = extract64(i, b + 12 * 4, 4);
+
+ t0 = rot_cell(i8, 1) ^ rot_cell(i4, 2) ^ rot_cell(i0, 1);
+ t1 = rot_cell(ic, 1) ^ rot_cell(i4, 1) ^ rot_cell(i0, 2);
+ t2 = rot_cell(ic, 2) ^ rot_cell(i8, 1) ^ rot_cell(i0, 1);
+ t3 = rot_cell(ic, 1) ^ rot_cell(i8, 2) ^ rot_cell(i4, 1);
+
+ o |= (uint64_t)t3 << b;
+ o |= (uint64_t)t2 << (b + 4 * 4);
+ o |= (uint64_t)t1 << (b + 8 * 4);
+ o |= (uint64_t)t0 << (b + 12 * 4);
+ }
+ return o;
+}
+
+static uint64_t tweak_cell_rot(uint64_t cell)
+{
+ return (cell >> 1) | (((cell ^ (cell >> 1)) & 1) << 3);
+}
+
+static uint64_t tweak_shuffle(uint64_t i)
+{
+ uint64_t o = 0;
+
+ o |= extract64(i, 16, 4) << 0;
+ o |= extract64(i, 20, 4) << 4;
+ o |= tweak_cell_rot(extract64(i, 24, 4)) << 8;
+ o |= extract64(i, 28, 4) << 12;
+
+ o |= tweak_cell_rot(extract64(i, 44, 4)) << 16;
+ o |= extract64(i, 8, 4) << 20;
+ o |= extract64(i, 12, 4) << 24;
+ o |= tweak_cell_rot(extract64(i, 32, 4)) << 28;
+
+ o |= extract64(i, 48, 4) << 32;
+ o |= extract64(i, 52, 4) << 36;
+ o |= extract64(i, 56, 4) << 40;
+ o |= tweak_cell_rot(extract64(i, 60, 4)) << 44;
+
+ o |= tweak_cell_rot(extract64(i, 0, 4)) << 48;
+ o |= extract64(i, 4, 4) << 52;
+ o |= tweak_cell_rot(extract64(i, 40, 4)) << 56;
+ o |= tweak_cell_rot(extract64(i, 36, 4)) << 60;
+
+ return o;
+}
+
+static uint64_t tweak_cell_inv_rot(uint64_t cell)
+{
+ return ((cell << 1) & 0xf) | ((cell & 1) ^ (cell >> 3));
+}
+
+static uint64_t tweak_inv_shuffle(uint64_t i)
+{
+ uint64_t o = 0;
+
+ o |= tweak_cell_inv_rot(extract64(i, 48, 4));
+ o |= extract64(i, 52, 4) << 4;
+ o |= extract64(i, 20, 4) << 8;
+ o |= extract64(i, 24, 4) << 12;
+
+ o |= extract64(i, 0, 4) << 16;
+ o |= extract64(i, 4, 4) << 20;
+ o |= tweak_cell_inv_rot(extract64(i, 8, 4)) << 24;
+ o |= extract64(i, 12, 4) << 28;
+
+ o |= tweak_cell_inv_rot(extract64(i, 28, 4)) << 32;
+ o |= tweak_cell_inv_rot(extract64(i, 60, 4)) << 36;
+ o |= tweak_cell_inv_rot(extract64(i, 56, 4)) << 40;
+ o |= tweak_cell_inv_rot(extract64(i, 16, 4)) << 44;
+
+ o |= extract64(i, 32, 4) << 48;
+ o |= extract64(i, 36, 4) << 52;
+ o |= extract64(i, 40, 4) << 56;
+ o |= tweak_cell_inv_rot(extract64(i, 44, 4)) << 60;
+
+ return o;
+}
+
static uint64_t pauth_computepac(uint64_t data, uint64_t modifier,
ARMPACKey key)
{
- g_assert_not_reached(); /* FIXME */
+ static const uint64_t RC[5] = {
+ 0x0000000000000000ull,
+ 0x13198A2E03707344ull,
+ 0xA4093822299F31D0ull,
+ 0x082EFA98EC4E6C89ull,
+ 0x452821E638D01377ull,
+ };
+ const uint64_t alpha = 0xC0AC29B7C97C50DDull;
+ /*
+ * Note that in the ARM pseudocode, key0 contains bits <127:64>
+ * and key1 contains bits <63:0> of the 128-bit key.
+ */
+ uint64_t key0 = key.hi, key1 = key.lo;
+ uint64_t workingval, runningmod, roundkey, modk0;
+ int i;
+
+ modk0 = (key0 << 63) | ((key0 >> 1) ^ (key0 >> 63));
+ runningmod = modifier;
+ workingval = data ^ key0;
+
+ for (i = 0; i <= 4; ++i) {
+ roundkey = key1 ^ runningmod;
+ workingval ^= roundkey;
+ workingval ^= RC[i];
+ if (i > 0) {
+ workingval = pac_cell_shuffle(workingval);
+ workingval = pac_mult(workingval);
+ }
+ workingval = pac_sub(workingval);
+ runningmod = tweak_shuffle(runningmod);
+ }
+ roundkey = modk0 ^ runningmod;
+ workingval ^= roundkey;
+ workingval = pac_cell_shuffle(workingval);
+ workingval = pac_mult(workingval);
+ workingval = pac_sub(workingval);
+ workingval = pac_cell_shuffle(workingval);
+ workingval = pac_mult(workingval);
+ workingval ^= key1;
+ workingval = pac_cell_inv_shuffle(workingval);
+ workingval = pac_inv_sub(workingval);
+ workingval = pac_mult(workingval);
+ workingval = pac_cell_inv_shuffle(workingval);
+ workingval ^= key0;
+ workingval ^= runningmod;
+ for (i = 0; i <= 4; ++i) {
+ workingval = pac_inv_sub(workingval);
+ if (i < 4) {
+ workingval = pac_mult(workingval);
+ workingval = pac_cell_inv_shuffle(workingval);
+ }
+ runningmod = tweak_inv_shuffle(runningmod);
+ roundkey = key1 ^ runningmod;
+ workingval ^= RC[4 - i];
+ workingval ^= roundkey;
+ workingval ^= alpha;
+ }
+ workingval ^= modk0;
+
+ return workingval;
}
static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
--
2.20.1
next prev parent reply other threads:[~2019-01-18 14:58 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-18 14:57 [Qemu-devel] [PULL 00/49] target-arm queue Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 01/49] hw/char/stm32f2xx_usart: Do not update data register when device is disabled Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 02/49] hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 03/49] target/arm: Allow Aarch32 exception return to switch from Mon->Hyp Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 04/49] ftgmac100: implement the new MDIO interface on Aspeed SoC Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 05/49] target/arm: Add state for the ARMv8.3-PAuth extension Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 06/49] target/arm: Add SCTLR bits through ARMv8.5 Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 07/49] target/arm: Add PAuth active bit to tbflags Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 08/49] target/arm: Introduce raise_exception_ra Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 09/49] target/arm: Add PAuth helpers Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 10/49] target/arm: Decode PAuth within system hint space Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 11/49] target/arm: Rearrange decode in disas_data_proc_1src Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 12/49] target/arm: Decode PAuth within disas_data_proc_1src Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 13/49] target/arm: Decode PAuth within disas_data_proc_2src Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 14/49] target/arm: Move helper_exception_return to helper-a64.c Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 15/49] target/arm: Add new_pc argument to helper_exception_return Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 16/49] target/arm: Rearrange decode in disas_uncond_b_reg Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 17/49] target/arm: Decode PAuth within disas_uncond_b_reg Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 18/49] target/arm: Decode Load/store register (pac) Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 19/49] target/arm: Move cpu_mmu_index out of line Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 20/49] target/arm: Introduce arm_mmu_idx Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 21/49] target/arm: Introduce arm_stage1_mmu_idx Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 22/49] target/arm: Create ARMVAParameters and helpers Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 23/49] target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 24/49] target/arm: Export aa64_va_parameters to internals.h Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 25/49] target/arm: Add aa64_va_parameters_both Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 26/49] target/arm: Decode TBID from TCR Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 27/49] target/arm: Reuse aa64_va_parameters for setting tbflags Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 28/49] target/arm: Implement pauth_strip Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 29/49] target/arm: Implement pauth_auth Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 30/49] target/arm: Implement pauth_addpac Peter Maydell
2019-01-18 14:57 ` Peter Maydell [this message]
2019-01-18 14:57 ` [Qemu-devel] [PULL 32/49] target/arm: Add PAuth system registers Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 33/49] target/arm: Enable PAuth for -cpu max Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 34/49] target/arm: Enable PAuth for user-only Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 35/49] target/arm: Tidy TBI handling in gen_a64_set_pc Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 36/49] migration: Add post_save function to VMStateDescription Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 37/49] target/arm: Reorganize PMCCNTR accesses Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 38/49] target/arm: Swap PMU values before/after migrations Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 39/49] target/arm: Filter cycle counter based on PMCCFILTR_EL0 Peter Maydell
2020-08-24 16:33 ` Peter Maydell
2020-08-25 14:41 ` Aaron Lindsay
2020-08-25 14:48 ` [PATCH] target/arm: Count PMU events when MDCR.SPME is set Aaron Lindsay
2020-09-11 14:13 ` Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 40/49] target/arm: Allow AArch32 access for PMCCFILTR Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 41/49] target/arm: Implement PMOVSSET Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 42/49] target/arm: Define FIELDs for ID_DFR0 Peter Maydell
2019-01-18 14:57 ` [Qemu-devel] [PULL 43/49] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 44/49] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 45/49] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 46/49] target/arm: PMU: Add instruction and cycle events Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 47/49] target/arm: PMU: Set PMCR.N to 4 Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 48/49] target/arm: Implement PMSWINC Peter Maydell
2019-01-18 14:58 ` [Qemu-devel] [PULL 49/49] tests/libqtest: Introduce qtest_init_with_serial() Peter Maydell
2019-01-31 17:48 ` [Qemu-devel] [PULL 00/49] target-arm queue no-reply
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