From: Yoshinori Sato <ysato@users.sourceforge.jp>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org,
Richard Henderson <richard.henderson@linaro.org>,
Yoshinori Sato <ysato@users.sourceforge.jp>,
philmd@redhat.com
Subject: [Qemu-devel] [PATCH v20 10/24] target/rx: Emit all disassembly in one prt()
Date: Sun, 16 Jun 2019 23:28:22 +0900 [thread overview]
Message-ID: <20190616142836.10614-11-ysato@users.sourceforge.jp> (raw)
In-Reply-To: <20190616142836.10614-1-ysato@users.sourceforge.jp>
From: Richard Henderson <richard.henderson@linaro.org>
Many of the multi-part prints have been eliminated by previous
patches. Eliminate the rest of them.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <20190607091116.49044-22-ysato@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/rx/disas.c | 75 +++++++++++++++++++++++++++++--------------------------
1 file changed, 39 insertions(+), 36 deletions(-)
diff --git a/target/rx/disas.c b/target/rx/disas.c
index db10385fd0..ebc1a44249 100644
--- a/target/rx/disas.c
+++ b/target/rx/disas.c
@@ -228,24 +228,21 @@ static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a)
/* mov.[bwl] rs,rd */
static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a)
{
- char dspd[8], dsps[8];
+ char dspd[8], dsps[8], szc = size[a->sz];
- prt("mov.%c\t", size[a->sz]);
if (a->lds == 3 && a->ldd == 3) {
/* mov.[bwl] rs,rd */
- prt("r%d, r%d", a->rs, a->rd);
- return true;
- }
- if (a->lds == 3) {
+ prt("mov.%c\tr%d, r%d", szc, a->rs, a->rd);
+ } else if (a->lds == 3) {
rx_index_addr(ctx, dspd, a->ldd, a->sz);
- prt("r%d, %s[r%d]", a->rs, dspd, a->rd);
+ prt("mov.%c\tr%d, %s[r%d]", szc, a->rs, dspd, a->rd);
} else if (a->ldd == 3) {
rx_index_addr(ctx, dsps, a->lds, a->sz);
- prt("%s[r%d], r%d", dsps, a->rs, a->rd);
+ prt("mov.%c\t%s[r%d], r%d", szc, dsps, a->rs, a->rd);
} else {
rx_index_addr(ctx, dsps, a->lds, a->sz);
rx_index_addr(ctx, dspd, a->ldd, a->sz);
- prt("%s[r%d], %s[r%d]", dsps, a->rs, dspd, a->rd);
+ prt("mov.%c\t%s[r%d], %s[r%d]", szc, dsps, a->rs, dspd, a->rd);
}
return true;
}
@@ -254,8 +251,11 @@ static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a)
/* mov.[bwl] rs,[-rd] */
static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a)
{
- prt("mov.%c\tr%d, ", size[a->sz], a->rs);
- prt((a->ad == 0) ? "[r%d+]" : "[-r%d]", a->rd);
+ if (a->ad) {
+ prt("mov.%c\tr%d, [-r%d]", size[a->sz], a->rs, a->rd);
+ } else {
+ prt("mov.%c\tr%d, [r%d+]", size[a->sz], a->rs, a->rd);
+ }
return true;
}
@@ -263,9 +263,11 @@ static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a)
/* mov.[bwl] [-rd],rs */
static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr *a)
{
- prt("mov.%c\t", size[a->sz]);
- prt((a->ad == 0) ? "[r%d+]" : "[-r%d]", a->rd);
- prt(", r%d", a->rs);
+ if (a->ad) {
+ prt("mov.%c\t[-r%d], r%d", size[a->sz], a->rd, a->rs);
+ } else {
+ prt("mov.%c\t[r%d+], r%d", size[a->sz], a->rd, a->rs);
+ }
return true;
}
@@ -299,9 +301,11 @@ static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_ar *a)
/* movu.[bw] [-rs],rd */
static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_pr *a)
{
- prt("movu.%c\t", size[a->sz]);
- prt((a->ad == 0) ? "[r%d+]" : "[-r%d]", a->rd);
- prt(", r%d", a->rs);
+ if (a->ad) {
+ prt("movu.%c\t[-r%d], r%d", size[a->sz], a->rd, a->rs);
+ } else {
+ prt("movu.%c\t[r%d+], r%d", size[a->sz], a->rd, a->rs);
+ }
return true;
}
@@ -478,11 +482,11 @@ static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr *a)
/* not rs, rd */
static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr *a)
{
- prt("not\t");
if (a->rs != a->rd) {
- prt("r%d, ", a->rs);
+ prt("not\tr%d, r%d", a->rs, a->rd);
+ } else {
+ prt("not\tr%d", a->rs);
}
- prt("r%d", a->rd);
return true;
}
@@ -490,11 +494,11 @@ static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr *a)
/* neg rs, rd */
static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a)
{
- prt("neg\t");
if (a->rs != a->rd) {
- prt("r%d, ", a->rs);
+ prt("neg\tr%d, r%d", a->rs, a->rd);
+ } else {
+ prt("neg\tr%d", a->rs);
}
- prt("r%d", a->rd);
return true;
}
@@ -606,11 +610,10 @@ static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a)
/* abs rs, rd */
static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a)
{
- prt("abs\t");
- if (a->rs == a->rd) {
- prt("r%d", a->rd);
+ if (a->rs != a->rd) {
+ prt("abs\tr%d, r%d", a->rs, a->rd);
} else {
- prt("r%d, r%d", a->rs, a->rd);
+ prt("abs\tr%d", a->rs);
}
return true;
}
@@ -733,11 +736,11 @@ static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU_mr *a)
/* shll #imm:5, rs, rd */
static bool trans_SHLL_irr(DisasContext *ctx, arg_SHLL_irr *a)
{
- prt("shll\t#%d, ", a->imm);
if (a->rs2 != a->rd) {
- prt("r%d, ", a->rs2);
+ prt("shll\t#%d, r%d, r%d", a->imm, a->rs2, a->rd);
+ } else {
+ prt("shll\t#%d, r%d", a->imm, a->rd);
}
- prt("r%d", a->rd);
return true;
}
@@ -752,11 +755,11 @@ static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a)
/* shar #imm:5, rs, rd */
static bool trans_SHAR_irr(DisasContext *ctx, arg_SHAR_irr *a)
{
- prt("shar\t#%d,", a->imm);
if (a->rs2 != a->rd) {
- prt("r%d, ", a->rs2);
+ prt("shar\t#%d, r%d, r%d", a->imm, a->rs2, a->rd);
+ } else {
+ prt("shar\t#%d, r%d", a->imm, a->rd);
}
- prt("r%d", a->rd);
return true;
}
@@ -771,11 +774,11 @@ static bool trans_SHAR_rr(DisasContext *ctx, arg_SHAR_rr *a)
/* shlr #imm:5, rs, rd */
static bool trans_SHLR_irr(DisasContext *ctx, arg_SHLR_irr *a)
{
- prt("shlr\t#%d, ", a->imm);
if (a->rs2 != a->rd) {
- prt("r%d, ", a->rs2);
+ prt("shlr\t#%d, r%d, r%d", a->imm, a->rs2, a->rd);
+ } else {
+ prt("shlr\t#%d, r%d", a->imm, a->rd);
}
- prt("r%d", a->rd);
return true;
}
--
2.11.0
next prev parent reply other threads:[~2019-06-16 14:42 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-16 14:28 [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 01/24] target/rx: TCG translation Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 02/24] target/rx: TCG helper Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 03/24] target/rx: CPU definition Yoshinori Sato
2019-06-16 18:13 ` Igor Mammedov
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 04/24] target/rx: Follow the change of tcg Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 05/24] target/rx: simplify rx_cpu_class_by_name Yoshinori Sato
2019-06-16 18:33 ` Igor Mammedov
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 06/24] target/rx: RX disassembler Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 07/24] target/rx: Disassemble rx_index_addr into a string Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 08/24] target/rx: Replace operand with prt_ldmi in disassembler Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 09/24] target/rx: Use prt_ldmi for XCHG_mr disassembly Yoshinori Sato
2019-06-16 14:28 ` Yoshinori Sato [this message]
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 11/24] target/rx: Collect all bytes during disassembly Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 12/24] target/rx: Dump bytes for each insn " Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 13/24] hw/intc: RX62N interrupt controller (ICUa) Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 14/24] hw/timer: RX62N internal timer modules Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 15/24] hw/char: RX62N serial communication interface (SCI) Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 16/24] hw/rx: RX Target hardware definition Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 17/24] target/rx: Move rx_load_image to rx-virt Yoshinori Sato
2019-06-16 18:49 ` Igor Mammedov
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 18/24] hw/rx: Honor -accel qtest Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 19/24] hw/rx: Restrict the RX62N microcontroller to the RX62N CPU core Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 20/24] qemu/bitops.h: Add extract8 and extract16 Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 21/24] hw/registerfields.h: Add 8bit and 16bit register macros Yoshinori Sato
2019-06-16 19:06 ` Igor Mammedov
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 22/24] Add rx-softmmu Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 23/24] MAINTAINERS: Add RX Yoshinori Sato
2019-06-16 14:28 ` [Qemu-devel] [PATCH v20 24/24] BootLinuxConsoleTest: Test the RX-Virt machine Yoshinori Sato
2019-06-16 15:18 ` [Qemu-devel] [PATCH v20 00/24] Add RX archtecture support no-reply
2019-06-16 19:08 ` Igor Mammedov
2019-06-16 15:55 ` no-reply
2019-06-16 16:45 ` no-reply
2019-06-16 17:26 ` no-reply
2019-06-16 17:33 ` no-reply
2019-06-16 18:00 ` no-reply
2019-06-16 18:18 ` no-reply
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