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From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: "Cédric Le Goater" <clg@kaod.org>,
	qemu-ppc@nongnu.org, "Greg Kurz" <groug@kaod.org>,
	qemu-devel@nongnu.org
Subject: [PATCH for-5.0 v5 08/23] ppc/xive: Introduce a XivePresenter interface
Date: Fri, 15 Nov 2019 17:24:21 +0100	[thread overview]
Message-ID: <20191115162436.30548-9-clg@kaod.org> (raw)
In-Reply-To: <20191115162436.30548-1-clg@kaod.org>

When the XIVE IVRE sub-engine (XiveRouter) looks for a Notification
Virtual Target (NVT) to notify, it broadcasts a message on the
PowerBUS to find an XIVE IVPE sub-engine (Presenter) with the NVT
dispatched on one of its HW threads, and then forwards the
notification if any response was received.

The current XIVE presenter model is sufficient for the pseries machine
because it has a single interrupt controller device, but the PowerNV
machine can have multiple chips each having its own interrupt
controller. In this case, the XIVE presenter model is too simple and
the CAM line matching should scan all chips of the system.

To start fixing this issue, we first extend the XIVE Router model with
a new XivePresenter QOM interface representing the XIVE IVPE
sub-engine. This interface exposes a 'match_nvt' handler which the
sPAPR and PowerNV XIVE Router models will need to implement to perform
the CAM line matching.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/ppc/xive.h | 32 ++++++++++++++++++++++++++++++++
 hw/intc/xive.c        | 26 +++++++++++++++++---------
 2 files changed, 49 insertions(+), 9 deletions(-)

diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index fa7adf87feb2..f9aa0fa0dac3 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -367,6 +367,38 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
 XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs);
 void xive_router_notify(XiveNotifier *xn, uint32_t lisn);
 
+/*
+ * XIVE Presenter
+ */
+
+typedef struct XiveTCTXMatch {
+    XiveTCTX *tctx;
+    uint8_t ring;
+} XiveTCTXMatch;
+
+typedef struct XivePresenter XivePresenter;
+
+#define TYPE_XIVE_PRESENTER "xive-presenter"
+#define XIVE_PRESENTER(obj)                                     \
+    INTERFACE_CHECK(XivePresenter, (obj), TYPE_XIVE_PRESENTER)
+#define XIVE_PRESENTER_CLASS(klass)                                     \
+    OBJECT_CLASS_CHECK(XivePresenterClass, (klass), TYPE_XIVE_PRESENTER)
+#define XIVE_PRESENTER_GET_CLASS(obj)                                   \
+    OBJECT_GET_CLASS(XivePresenterClass, (obj), TYPE_XIVE_PRESENTER)
+
+typedef struct XivePresenterClass {
+    InterfaceClass parent;
+    int (*match_nvt)(XivePresenter *xptr, uint8_t format,
+                     uint8_t nvt_blk, uint32_t nvt_idx,
+                     bool cam_ignore, uint8_t priority,
+                     uint32_t logic_serv, XiveTCTXMatch *match);
+} XivePresenterClass;
+
+int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
+                              uint8_t format,
+                              uint8_t nvt_blk, uint32_t nvt_idx,
+                              bool cam_ignore, uint32_t logic_serv);
+
 /*
  * XIVE END ESBs
  */
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 511e1a936347..344bb3f3bc4b 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1363,9 +1363,10 @@ static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx)
 /*
  * The thread context register words are in big-endian format.
  */
-static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format,
-                                     uint8_t nvt_blk, uint32_t nvt_idx,
-                                     bool cam_ignore, uint32_t logic_serv)
+int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
+                              uint8_t format,
+                              uint8_t nvt_blk, uint32_t nvt_idx,
+                              bool cam_ignore, uint32_t logic_serv)
 {
     uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx);
     uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]);
@@ -1422,11 +1423,6 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format,
     return -1;
 }
 
-typedef struct XiveTCTXMatch {
-    XiveTCTX *tctx;
-    uint8_t ring;
-} XiveTCTXMatch;
-
 static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
                                  uint8_t nvt_blk, uint32_t nvt_idx,
                                  bool cam_ignore, uint8_t priority,
@@ -1460,7 +1456,8 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
          * Check the thread context CAM lines and record matches. We
          * will handle CPU exception delivery later
          */
-        ring = xive_presenter_tctx_match(tctx, format, nvt_blk, nvt_idx,
+        ring = xive_presenter_tctx_match(XIVE_PRESENTER(xrtr), tctx, format,
+                                         nvt_blk, nvt_idx,
                                          cam_ignore, logic_serv);
         /*
          * Save the context and follow on to catch duplicates, that we
@@ -1754,6 +1751,7 @@ static const TypeInfo xive_router_info = {
     .class_init    = xive_router_class_init,
     .interfaces    = (InterfaceInfo[]) {
         { TYPE_XIVE_NOTIFIER },
+        { TYPE_XIVE_PRESENTER },
         { }
     }
 };
@@ -1923,10 +1921,20 @@ static const TypeInfo xive_notifier_info = {
     .class_size = sizeof(XiveNotifierClass),
 };
 
+/*
+ * XIVE Presenter
+ */
+static const TypeInfo xive_presenter_info = {
+    .name = TYPE_XIVE_PRESENTER,
+    .parent = TYPE_INTERFACE,
+    .class_size = sizeof(XivePresenterClass),
+};
+
 static void xive_register_types(void)
 {
     type_register_static(&xive_source_info);
     type_register_static(&xive_notifier_info);
+    type_register_static(&xive_presenter_info);
     type_register_static(&xive_router_info);
     type_register_static(&xive_end_source_info);
     type_register_static(&xive_tctx_info);
-- 
2.21.0



  parent reply	other threads:[~2019-11-15 16:39 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-15 16:24 [PATCH for-5.0 v5 00/23] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 01/23] ppc/xive: Record the IPB in the associated NVT Cédric Le Goater
2019-11-18 15:44   ` Greg Kurz
2019-11-18 15:57     ` Cédric Le Goater
2019-11-19  3:18   ` David Gibson
2019-11-15 16:24 ` [PATCH for-5.0 v5 02/23] ppc/xive: Introduce helpers for the NVT id Cédric Le Goater
2019-11-19  3:19   ` David Gibson
2019-11-19 14:04   ` Greg Kurz
2019-11-19 16:12     ` Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 03/23] ppc/pnv: Remove pnv_xive_vst_size() routine Cédric Le Goater
2019-11-19  3:22   ` David Gibson
2019-11-15 16:24 ` [PATCH for-5.0 v5 04/23] ppc/pnv: Dump the XIVE NVT table Cédric Le Goater
2019-11-19 22:06   ` David Gibson
2019-11-20  8:39     ` Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 05/23] ppc/pnv: Quiesce some XIVE errors Cédric Le Goater
2019-11-19 22:07   ` David Gibson
2019-11-15 16:24 ` [PATCH for-5.0 v5 06/23] ppc/xive: Introduce OS CAM line helpers Cédric Le Goater
2019-11-20  3:24   ` David Gibson
2019-11-15 16:24 ` [PATCH for-5.0 v5 07/23] ppc/xive: Check V bit in TM_PULL_POOL_CTX Cédric Le Goater
2019-11-20  3:25   ` David Gibson
2019-11-15 16:24 ` Cédric Le Goater [this message]
2019-11-20  9:35   ` [PATCH for-5.0 v5 08/23] ppc/xive: Introduce a XivePresenter interface Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 09/23] ppc/xive: Implement the " Cédric Le Goater
2019-11-20 10:18   ` Greg Kurz
2019-11-20 10:45     ` Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 10/23] ppc/pnv: Loop on the threads of the chip to find a matching NVT Cédric Le Goater
2019-11-20 16:13   ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 11/23] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper Cédric Le Goater
2019-11-20 17:26   ` Greg Kurz
2019-11-20 21:40     ` Cédric Le Goater
2019-11-21  7:58       ` Greg Kurz
2019-11-21  9:16         ` Cédric Le Goater
2019-11-21  9:49           ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 12/23] ppc/xive: Introduce a XiveFabric interface Cédric Le Goater
2019-11-20 17:27   ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 13/23] ppc/pnv: Implement the " Cédric Le Goater
2019-11-20 17:41   ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 14/23] ppc/spapr: " Cédric Le Goater
2019-11-20 17:53   ` Greg Kurz
2019-11-21  6:56     ` Cédric Le Goater
2019-11-21  7:24       ` Greg Kurz
2019-11-21  7:38         ` Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 15/23] ppc/xive: Use the XiveFabric and XivePresenter interfaces Cédric Le Goater
2019-11-20 18:30   ` Greg Kurz
2019-11-21  7:01     ` Cédric Le Goater
2019-11-21  7:30       ` Greg Kurz
2019-11-21  7:40         ` Cédric Le Goater
2019-11-21  8:08           ` Greg Kurz
2019-11-21  9:22             ` Cédric Le Goater
2019-11-21  9:56               ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 16/23] ppc/xive: Extend the TIMA operation with a XivePresenter parameter Cédric Le Goater
2019-11-22 10:16   ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 17/23] ppc/pnv: Clarify how the TIMA is accessed on a multichip system Cédric Le Goater
2019-11-22 13:54   ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 18/23] ppc/xive: Move the TIMA operations to the controller model Cédric Le Goater
2019-11-22 14:58   ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 19/23] ppc/xive: Remove the get_tctx() XiveRouter handler Cédric Le Goater
2019-11-22 14:07   ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 20/23] ppc/xive: Introduce a xive_tctx_ipb_update() helper Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 21/23] ppc/xive: Synthesize interrupt from the saved IPB in the NVT Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 22/23] ppc/pnv: Introduce a pnv_xive_block_id() helper Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 23/23] ppc/pnv: Extend XiveRouter with a get_block_id() handler Cédric Le Goater
2019-11-22 18:17 ` [PATCH for-5.0 v5 00/23] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
2019-11-23  9:25   ` David Gibson

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