From: "Cédric Le Goater" <clg@kaod.org>
To: Greg Kurz <groug@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
David Gibson <david@gibson.dropbear.id.au>
Subject: Re: [PATCH for-5.0 v5 09/23] ppc/xive: Implement the XivePresenter interface
Date: Wed, 20 Nov 2019 11:45:30 +0100 [thread overview]
Message-ID: <625d0e83-671a-8d28-0b90-2f004bab30f7@kaod.org> (raw)
In-Reply-To: <20191120111852.6bd519c2@bahia.lan>
On 20/11/2019 11:18, Greg Kurz wrote:
> On Fri, 15 Nov 2019 17:24:22 +0100
> Cédric Le Goater <clg@kaod.org> wrote:
>
>> Each XIVE Router model, sPAPR and PowerNV, now implements the 'match_nvt'
>> handler of the XivePresenter QOM interface. This is simply moving code
>> and taking into account the new API.
>>
>> To be noted that the xive_router_get_tctx() helper is not used anymore
>> when doing CAM matching and will be removed later on after other changes.
>>
>> The XIVE presenter model is still too simple for the PowerNV machine
>> and the CAM matching algo is not correct on multichip system. Subsequent
>> patches will introduce more changes to scan all chips of the system.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> hw/intc/pnv_xive.c | 41 +++++++++++++++++++++++++++++++++++
>> hw/intc/spapr_xive.c | 49 ++++++++++++++++++++++++++++++++++++++++++
>> hw/intc/xive.c | 51 ++++++--------------------------------------
>> 3 files changed, 97 insertions(+), 44 deletions(-)
>>
>> diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
>> index a394331ddd6a..087cbfbaad48 100644
>> --- a/hw/intc/pnv_xive.c
>> +++ b/hw/intc/pnv_xive.c
>> @@ -372,6 +372,45 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
>> return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas);
>> }
>>
>> +static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
>> + uint8_t nvt_blk, uint32_t nvt_idx,
>> + bool cam_ignore, uint8_t priority,
>> + uint32_t logic_serv, XiveTCTXMatch *match)
>> +{
>> + CPUState *cs;
>> + int count = 0;
>> +
>> + CPU_FOREACH(cs) {
>> + PowerPCCPU *cpu = POWERPC_CPU(cs);
>> + XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
>> + int ring;
>> +
>
> I guess it's ok not to check tctx here because the powernv machine type
> doesn't support cpu hotplug.
patch 10 and patch 11 add some more changes in that area.
C.
>
> LGTM despite the non-strict CamelCase type :)
>
> Reviewed-by: Greg Kurz <groug@kaod.org>
>
>> + /*
>> + * Check the thread context CAM lines and record matches.
>> + */
>> + ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nvt_idx,
>> + cam_ignore, logic_serv);
>> + /*
>> + * Save the context and follow on to catch duplicates, that we
>> + * don't support yet.
>> + */
>> + if (ring != -1) {
>> + if (match->tctx) {
>> + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a "
>> + "thread context NVT %x/%x\n",
>> + nvt_blk, nvt_idx);
>> + return -1;
>> + }
>> +
>> + match->ring = ring;
>> + match->tctx = tctx;
>> + count++;
>> + }
>> + }
>> +
>> + return count;
>> +}
>> +
>> static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
>> {
>> PowerPCCPU *cpu = POWERPC_CPU(cs);
>> @@ -1810,6 +1849,7 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data)
>> PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
>> XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass);
>> XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass);
>> + XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass);
>>
>> xdc->dt_xscom = pnv_xive_dt_xscom;
>>
>> @@ -1825,6 +1865,7 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data)
>> xrc->get_tctx = pnv_xive_get_tctx;
>>
>> xnc->notify = pnv_xive_notify;
>> + xpc->match_nvt = pnv_xive_match_nvt;
>> };
>>
>> static const TypeInfo pnv_xive_info = {
>> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
>> index 729246e906c9..bb3b2dfdb77f 100644
>> --- a/hw/intc/spapr_xive.c
>> +++ b/hw/intc/spapr_xive.c
>> @@ -405,6 +405,52 @@ static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
>> return spapr_cpu_state(cpu)->tctx;
>> }
>>
>> +static int spapr_xive_match_nvt(XivePresenter *xptr, uint8_t format,
>> + uint8_t nvt_blk, uint32_t nvt_idx,
>> + bool cam_ignore, uint8_t priority,
>> + uint32_t logic_serv, XiveTCTXMatch *match)
>> +{
>> + CPUState *cs;
>> + int count = 0;
>> +
>> + CPU_FOREACH(cs) {
>> + PowerPCCPU *cpu = POWERPC_CPU(cs);
>> + XiveTCTX *tctx = spapr_cpu_state(cpu)->tctx;
>> + int ring;
>> +
>> + /*
>> + * Skip partially initialized vCPUs. This can happen when
>> + * vCPUs are hotplugged.
>> + */
>> + if (!tctx) {
>> + continue;
>> + }
>> +
>> + /*
>> + * Check the thread context CAM lines and record matches.
>> + */
>> + ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, nvt_idx,
>> + cam_ignore, logic_serv);
>> + /*
>> + * Save the matching thread interrupt context and follow on to
>> + * check for duplicates which are invalid.
>> + */
>> + if (ring != -1) {
>> + if (match->tctx) {
>> + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread "
>> + "context NVT %x/%x\n", nvt_blk, nvt_idx);
>> + return -1;
>> + }
>> +
>> + match->ring = ring;
>> + match->tctx = tctx;
>> + count++;
>> + }
>> + }
>> +
>> + return count;
>> +}
>> +
>> static const VMStateDescription vmstate_spapr_xive_end = {
>> .name = TYPE_SPAPR_XIVE "/end",
>> .version_id = 1,
>> @@ -684,6 +730,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
>> DeviceClass *dc = DEVICE_CLASS(klass);
>> XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass);
>> SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass);
>> + XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass);
>>
>> dc->desc = "sPAPR XIVE Interrupt Controller";
>> dc->props = spapr_xive_properties;
>> @@ -708,6 +755,8 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
>> sicc->print_info = spapr_xive_print_info;
>> sicc->dt = spapr_xive_dt;
>> sicc->post_load = spapr_xive_post_load;
>> +
>> + xpc->match_nvt = spapr_xive_match_nvt;
>> }
>>
>> static const TypeInfo spapr_xive_info = {
>> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
>> index 344bb3f3bc4b..da6196ca958f 100644
>> --- a/hw/intc/xive.c
>> +++ b/hw/intc/xive.c
>> @@ -1428,51 +1428,14 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
>> bool cam_ignore, uint8_t priority,
>> uint32_t logic_serv, XiveTCTXMatch *match)
>> {
>> - CPUState *cs;
>> + XivePresenter *xptr = XIVE_PRESENTER(xrtr);
>> + XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
>> + int count;
>>
>> - /*
>> - * TODO (PowerNV): handle chip_id overwrite of block field for
>> - * hardwired CAM compares
>> - */
>> -
>> - CPU_FOREACH(cs) {
>> - XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs);
>> - int ring;
>> -
>> - /*
>> - * Skip partially initialized vCPUs. This can happen when
>> - * vCPUs are hotplugged.
>> - */
>> - if (!tctx) {
>> - continue;
>> - }
>> -
>> - /*
>> - * HW checks that the CPU is enabled in the Physical Thread
>> - * Enable Register (PTER).
>> - */
>> -
>> - /*
>> - * Check the thread context CAM lines and record matches. We
>> - * will handle CPU exception delivery later
>> - */
>> - ring = xive_presenter_tctx_match(XIVE_PRESENTER(xrtr), tctx, format,
>> - nvt_blk, nvt_idx,
>> - cam_ignore, logic_serv);
>> - /*
>> - * Save the context and follow on to catch duplicates, that we
>> - * don't support yet.
>> - */
>> - if (ring != -1) {
>> - if (match->tctx) {
>> - qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a thread "
>> - "context NVT %x/%x\n", nvt_blk, nvt_idx);
>> - return false;
>> - }
>> -
>> - match->ring = ring;
>> - match->tctx = tctx;
>> - }
>> + count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
>> + priority, logic_serv, match);
>> + if (count < 0) {
>> + return false;
>> }
>>
>> if (!match->tctx) {
>
next prev parent reply other threads:[~2019-11-20 10:49 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-15 16:24 [PATCH for-5.0 v5 00/23] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 01/23] ppc/xive: Record the IPB in the associated NVT Cédric Le Goater
2019-11-18 15:44 ` Greg Kurz
2019-11-18 15:57 ` Cédric Le Goater
2019-11-19 3:18 ` David Gibson
2019-11-15 16:24 ` [PATCH for-5.0 v5 02/23] ppc/xive: Introduce helpers for the NVT id Cédric Le Goater
2019-11-19 3:19 ` David Gibson
2019-11-19 14:04 ` Greg Kurz
2019-11-19 16:12 ` Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 03/23] ppc/pnv: Remove pnv_xive_vst_size() routine Cédric Le Goater
2019-11-19 3:22 ` David Gibson
2019-11-15 16:24 ` [PATCH for-5.0 v5 04/23] ppc/pnv: Dump the XIVE NVT table Cédric Le Goater
2019-11-19 22:06 ` David Gibson
2019-11-20 8:39 ` Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 05/23] ppc/pnv: Quiesce some XIVE errors Cédric Le Goater
2019-11-19 22:07 ` David Gibson
2019-11-15 16:24 ` [PATCH for-5.0 v5 06/23] ppc/xive: Introduce OS CAM line helpers Cédric Le Goater
2019-11-20 3:24 ` David Gibson
2019-11-15 16:24 ` [PATCH for-5.0 v5 07/23] ppc/xive: Check V bit in TM_PULL_POOL_CTX Cédric Le Goater
2019-11-20 3:25 ` David Gibson
2019-11-15 16:24 ` [PATCH for-5.0 v5 08/23] ppc/xive: Introduce a XivePresenter interface Cédric Le Goater
2019-11-20 9:35 ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 09/23] ppc/xive: Implement the " Cédric Le Goater
2019-11-20 10:18 ` Greg Kurz
2019-11-20 10:45 ` Cédric Le Goater [this message]
2019-11-15 16:24 ` [PATCH for-5.0 v5 10/23] ppc/pnv: Loop on the threads of the chip to find a matching NVT Cédric Le Goater
2019-11-20 16:13 ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 11/23] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper Cédric Le Goater
2019-11-20 17:26 ` Greg Kurz
2019-11-20 21:40 ` Cédric Le Goater
2019-11-21 7:58 ` Greg Kurz
2019-11-21 9:16 ` Cédric Le Goater
2019-11-21 9:49 ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 12/23] ppc/xive: Introduce a XiveFabric interface Cédric Le Goater
2019-11-20 17:27 ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 13/23] ppc/pnv: Implement the " Cédric Le Goater
2019-11-20 17:41 ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 14/23] ppc/spapr: " Cédric Le Goater
2019-11-20 17:53 ` Greg Kurz
2019-11-21 6:56 ` Cédric Le Goater
2019-11-21 7:24 ` Greg Kurz
2019-11-21 7:38 ` Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 15/23] ppc/xive: Use the XiveFabric and XivePresenter interfaces Cédric Le Goater
2019-11-20 18:30 ` Greg Kurz
2019-11-21 7:01 ` Cédric Le Goater
2019-11-21 7:30 ` Greg Kurz
2019-11-21 7:40 ` Cédric Le Goater
2019-11-21 8:08 ` Greg Kurz
2019-11-21 9:22 ` Cédric Le Goater
2019-11-21 9:56 ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 16/23] ppc/xive: Extend the TIMA operation with a XivePresenter parameter Cédric Le Goater
2019-11-22 10:16 ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 17/23] ppc/pnv: Clarify how the TIMA is accessed on a multichip system Cédric Le Goater
2019-11-22 13:54 ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 18/23] ppc/xive: Move the TIMA operations to the controller model Cédric Le Goater
2019-11-22 14:58 ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 19/23] ppc/xive: Remove the get_tctx() XiveRouter handler Cédric Le Goater
2019-11-22 14:07 ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 20/23] ppc/xive: Introduce a xive_tctx_ipb_update() helper Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 21/23] ppc/xive: Synthesize interrupt from the saved IPB in the NVT Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 22/23] ppc/pnv: Introduce a pnv_xive_block_id() helper Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 23/23] ppc/pnv: Extend XiveRouter with a get_block_id() handler Cédric Le Goater
2019-11-22 18:17 ` [PATCH for-5.0 v5 00/23] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
2019-11-23 9:25 ` David Gibson
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