qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Cédric Le Goater" <clg@kaod.org>
To: Greg Kurz <groug@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	David Gibson <david@gibson.dropbear.id.au>
Subject: Re: [PATCH for-5.0 v5 14/23] ppc/spapr: Implement the XiveFabric interface
Date: Thu, 21 Nov 2019 08:38:53 +0100	[thread overview]
Message-ID: <68f509ee-e993-3a84-bc09-a00b591b2a4b@kaod.org> (raw)
In-Reply-To: <20191121082439.3ffdb02a@bahia.lan>

On 21/11/2019 08:24, Greg Kurz wrote:
> On Thu, 21 Nov 2019 07:56:32 +0100
> Cédric Le Goater <clg@kaod.org> wrote:
> 
>> On 20/11/2019 18:53, Greg Kurz wrote:
>>> On Fri, 15 Nov 2019 17:24:27 +0100
>>> Cédric Le Goater <clg@kaod.org> wrote:
>>>
>>>> The CAM line matching sequence in the pseries machine does not change
>>>> much apart from the use of the new QOM interfaces. There is an extra
>>>> indirection because of the sPAPR IRQ backend of the machine. Only the
>>>> XIVE backend implements the new 'match_nvt' handler.
>>>>
>>>
>>> The changelog needs an update since you dropped the indirection you had
>>> in v4.
>>
>> Indeed.
>>
>>>
>>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>>> ---
>>>>  hw/ppc/spapr.c | 36 ++++++++++++++++++++++++++++++++++++
>>>>  1 file changed, 36 insertions(+)
>>>>
>>>> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
>>>> index 94f9d27096af..a8f5850f65bb 100644
>>>> --- a/hw/ppc/spapr.c
>>>> +++ b/hw/ppc/spapr.c
>>>> @@ -4270,6 +4270,39 @@ static void spapr_pic_print_info(InterruptStatsProvider *obj,
>>>>                     kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
>>>>  }
>>>>  
>>>> +static int spapr_xive_match_nvt(XiveFabric *xfb, uint8_t format,
>>>> +                                uint8_t nvt_blk, uint32_t nvt_idx,
>>>> +                                bool cam_ignore, uint8_t priority,
>>>> +                                uint32_t logic_serv, XiveTCTXMatch *match)
>>>> +{
>>>> +    SpaprMachineState *spapr = SPAPR_MACHINE(xfb);
>>>> +    XivePresenter *xptr = XIVE_PRESENTER(spapr->xive);
>>>> +    XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
>>>> +    int count;
>>>> +
>>>
>>> As suggested by David, you should probably assert() that XIVE is in use
>>> for extra paran^Wsafety.
>>
>> I don't see the need. The stack call is clear enough IMO. It can only be 
>> reached from the XiveRouter.
>>
> 
> Hmm... the assert() proposal isn't about this getting called by some
> other code, it is about ensuring XIVE is the active IC in case the
> machine was started with ic-mode=dual. But if you're confident enough
> it can never ever happen, no matter any subsequent change may done to
> the code, then don't add it :)

If XIVE mode is not selected, the XIVE ESB pages are not mapped in the 
machine address space and you can not reach the Router without them.

C.

> 
>> Thanks,
>>
>> C. 
>>
>>> With these fixed,
>>>
>>> Reviewed-by: Greg Kurz <groug@kaod.org>
>>>
>>>> +    count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
>>>> +                           priority, logic_serv, match);
>>>> +    if (count < 0) {
>>>> +        return count;
>>>> +    }
>>>> +
>>>> +    /*
>>>> +     * When we implement the save and restore of the thread interrupt
>>>> +     * contexts in the enter/exit CPU handlers of the machine and the
>>>> +     * escalations in QEMU, we should be able to handle non dispatched
>>>> +     * vCPUs.
>>>> +     *
>>>> +     * Until this is done, the sPAPR machine should find at least one
>>>> +     * matching context always.
>>>> +     */
>>>> +    if (count == 0) {
>>>> +        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n",
>>>> +                      nvt_blk, nvt_idx);
>>>> +    }
>>>> +
>>>> +    return count;
>>>> +}
>>>> +
>>>>  int spapr_get_vcpu_id(PowerPCCPU *cpu)
>>>>  {
>>>>      return cpu->vcpu_id;
>>>> @@ -4366,6 +4399,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
>>>>      PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
>>>>      XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
>>>>      InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
>>>> +    XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
>>>>  
>>>>      mc->desc = "pSeries Logical Partition (PAPR compliant)";
>>>>      mc->ignore_boot_device_suffixes = true;
>>>> @@ -4442,6 +4476,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
>>>>      smc->linux_pci_probe = true;
>>>>      smc->smp_threads_vsmt = true;
>>>>      smc->nr_xirqs = SPAPR_NR_XIRQS;
>>>> +    xfc->match_nvt = spapr_xive_match_nvt;
>>>>  }
>>>>  
>>>>  static const TypeInfo spapr_machine_info = {
>>>> @@ -4460,6 +4495,7 @@ static const TypeInfo spapr_machine_info = {
>>>>          { TYPE_PPC_VIRTUAL_HYPERVISOR },
>>>>          { TYPE_XICS_FABRIC },
>>>>          { TYPE_INTERRUPT_STATS_PROVIDER },
>>>> +        { TYPE_XIVE_FABRIC },
>>>>          { }
>>>>      },
>>>>  };
>>>
>>
> 



  reply	other threads:[~2019-11-21  7:39 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-15 16:24 [PATCH for-5.0 v5 00/23] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 01/23] ppc/xive: Record the IPB in the associated NVT Cédric Le Goater
2019-11-18 15:44   ` Greg Kurz
2019-11-18 15:57     ` Cédric Le Goater
2019-11-19  3:18   ` David Gibson
2019-11-15 16:24 ` [PATCH for-5.0 v5 02/23] ppc/xive: Introduce helpers for the NVT id Cédric Le Goater
2019-11-19  3:19   ` David Gibson
2019-11-19 14:04   ` Greg Kurz
2019-11-19 16:12     ` Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 03/23] ppc/pnv: Remove pnv_xive_vst_size() routine Cédric Le Goater
2019-11-19  3:22   ` David Gibson
2019-11-15 16:24 ` [PATCH for-5.0 v5 04/23] ppc/pnv: Dump the XIVE NVT table Cédric Le Goater
2019-11-19 22:06   ` David Gibson
2019-11-20  8:39     ` Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 05/23] ppc/pnv: Quiesce some XIVE errors Cédric Le Goater
2019-11-19 22:07   ` David Gibson
2019-11-15 16:24 ` [PATCH for-5.0 v5 06/23] ppc/xive: Introduce OS CAM line helpers Cédric Le Goater
2019-11-20  3:24   ` David Gibson
2019-11-15 16:24 ` [PATCH for-5.0 v5 07/23] ppc/xive: Check V bit in TM_PULL_POOL_CTX Cédric Le Goater
2019-11-20  3:25   ` David Gibson
2019-11-15 16:24 ` [PATCH for-5.0 v5 08/23] ppc/xive: Introduce a XivePresenter interface Cédric Le Goater
2019-11-20  9:35   ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 09/23] ppc/xive: Implement the " Cédric Le Goater
2019-11-20 10:18   ` Greg Kurz
2019-11-20 10:45     ` Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 10/23] ppc/pnv: Loop on the threads of the chip to find a matching NVT Cédric Le Goater
2019-11-20 16:13   ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 11/23] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper Cédric Le Goater
2019-11-20 17:26   ` Greg Kurz
2019-11-20 21:40     ` Cédric Le Goater
2019-11-21  7:58       ` Greg Kurz
2019-11-21  9:16         ` Cédric Le Goater
2019-11-21  9:49           ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 12/23] ppc/xive: Introduce a XiveFabric interface Cédric Le Goater
2019-11-20 17:27   ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 13/23] ppc/pnv: Implement the " Cédric Le Goater
2019-11-20 17:41   ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 14/23] ppc/spapr: " Cédric Le Goater
2019-11-20 17:53   ` Greg Kurz
2019-11-21  6:56     ` Cédric Le Goater
2019-11-21  7:24       ` Greg Kurz
2019-11-21  7:38         ` Cédric Le Goater [this message]
2019-11-15 16:24 ` [PATCH for-5.0 v5 15/23] ppc/xive: Use the XiveFabric and XivePresenter interfaces Cédric Le Goater
2019-11-20 18:30   ` Greg Kurz
2019-11-21  7:01     ` Cédric Le Goater
2019-11-21  7:30       ` Greg Kurz
2019-11-21  7:40         ` Cédric Le Goater
2019-11-21  8:08           ` Greg Kurz
2019-11-21  9:22             ` Cédric Le Goater
2019-11-21  9:56               ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 16/23] ppc/xive: Extend the TIMA operation with a XivePresenter parameter Cédric Le Goater
2019-11-22 10:16   ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 17/23] ppc/pnv: Clarify how the TIMA is accessed on a multichip system Cédric Le Goater
2019-11-22 13:54   ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 18/23] ppc/xive: Move the TIMA operations to the controller model Cédric Le Goater
2019-11-22 14:58   ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 19/23] ppc/xive: Remove the get_tctx() XiveRouter handler Cédric Le Goater
2019-11-22 14:07   ` Greg Kurz
2019-11-15 16:24 ` [PATCH for-5.0 v5 20/23] ppc/xive: Introduce a xive_tctx_ipb_update() helper Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 21/23] ppc/xive: Synthesize interrupt from the saved IPB in the NVT Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 22/23] ppc/pnv: Introduce a pnv_xive_block_id() helper Cédric Le Goater
2019-11-15 16:24 ` [PATCH for-5.0 v5 23/23] ppc/pnv: Extend XiveRouter with a get_block_id() handler Cédric Le Goater
2019-11-22 18:17 ` [PATCH for-5.0 v5 00/23] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
2019-11-23  9:25   ` David Gibson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=68f509ee-e993-3a84-bc09-a00b591b2a4b@kaod.org \
    --to=clg@kaod.org \
    --cc=david@gibson.dropbear.id.au \
    --cc=groug@kaod.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).