qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: "Cédric Le Goater" <clg@kaod.org>,
	qemu-ppc@nongnu.org, "Greg Kurz" <groug@kaod.org>,
	qemu-devel@nongnu.org
Subject: [PATCH 6/9] ppc/pnv: Add a OCC model for POWER10
Date: Wed, 13 May 2020 17:11:06 +0200	[thread overview]
Message-ID: <20200513151109.453530-7-clg@kaod.org> (raw)
In-Reply-To: <20200513151109.453530-1-clg@kaod.org>

Needs some more refinements but this model does not do much anyhow.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/ppc/pnv.h       |  1 +
 include/hw/ppc/pnv_occ.h   |  2 ++
 include/hw/ppc/pnv_xscom.h |  3 +++
 hw/ppc/pnv.c               | 14 ++++++++++++++
 hw/ppc/pnv_occ.c           | 17 +++++++++++++++++
 5 files changed, 37 insertions(+)

diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index f318bb10add4..3ff610a9c7b5 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -122,6 +122,7 @@ typedef struct Pnv10Chip {
     PnvXive2     xive;
     Pnv9Psi      psi;
     PnvLpcController lpc;
+    PnvOCC       occ;
 } Pnv10Chip;
 
 #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
index f8d3061419dc..57cb437c9ca1 100644
--- a/include/hw/ppc/pnv_occ.h
+++ b/include/hw/ppc/pnv_occ.h
@@ -28,6 +28,8 @@
 #define PNV8_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV8_OCC)
 #define TYPE_PNV9_OCC TYPE_PNV_OCC "-POWER9"
 #define PNV9_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV9_OCC)
+#define TYPE_PNV10_OCC TYPE_PNV_OCC "-POWER10"
+#define PNV10_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV10_OCC)
 
 #define PNV_OCC_SENSOR_DATA_BLOCK_OFFSET 0x00580000
 #define PNV_OCC_SENSOR_DATA_BLOCK_SIZE   0x00025800
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 1211add3e79c..f26c5217764d 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -133,6 +133,9 @@ typedef struct PnvXScomInterfaceClass {
 #define PNV10_XSCOM_PSIHB_BASE     0x3011D00
 #define PNV10_XSCOM_PSIHB_SIZE     0x100
 
+#define PNV10_XSCOM_OCC_BASE       PNV_XSCOM_OCC_BASE
+#define PNV10_XSCOM_OCC_SIZE       0x8000
+
 #define PNV10_XSCOM_XIVE2_BASE     0x2010800
 #define PNV10_XSCOM_XIVE2_SIZE     0x400
 
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 73c40ce3209f..9f1698a74467 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1617,6 +1617,8 @@ static void pnv_chip_power10_instance_init(Object *obj)
                             TYPE_PNV10_PSI, &error_abort, NULL);
     object_initialize_child(obj, "lpc",  &chip10->lpc, sizeof(chip10->lpc),
                             TYPE_PNV10_LPC, &error_abort, NULL);
+    object_initialize_child(obj, "occ",  &chip10->occ, sizeof(chip10->occ),
+                            TYPE_PNV10_OCC, &error_abort, NULL);
 }
 
 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
@@ -1690,6 +1692,18 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
 
     chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
                                             (uint64_t) PNV10_LPCM_BASE(chip));
+
+    /* Create the simplified OCC model */
+    object_property_set_link(OBJECT(&chip10->occ), OBJECT(&chip10->psi), "psi",
+                             &error_abort);
+    object_property_set_bool(OBJECT(&chip10->occ), true, "realized",
+                             &local_err);
+    if (local_err) {
+        error_propagate(errp, local_err);
+        return;
+    }
+    pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
+                            &chip10->occ.xscom_regs);
 }
 
 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
index 5a716c256edc..7a2aea8fb9d1 100644
--- a/hw/ppc/pnv_occ.c
+++ b/hw/ppc/pnv_occ.c
@@ -249,6 +249,22 @@ static const TypeInfo pnv_occ_power9_type_info = {
     .class_init    = pnv_occ_power9_class_init,
 };
 
+static void pnv_occ_power10_class_init(ObjectClass *klass, void *data)
+{
+    PnvOCCClass *poc = PNV_OCC_CLASS(klass);
+
+    poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
+    poc->xscom_ops = &pnv_occ_power9_xscom_ops;
+    poc->psi_irq = PSIHB9_IRQ_OCC;
+}
+
+static const TypeInfo pnv_occ_power10_type_info = {
+    .name          = TYPE_PNV10_OCC,
+    .parent        = TYPE_PNV_OCC,
+    .instance_size = sizeof(PnvOCC),
+    .class_init    = pnv_occ_power10_class_init,
+};
+
 static void pnv_occ_realize(DeviceState *dev, Error **errp)
 {
     PnvOCC *occ = PNV_OCC(dev);
@@ -297,6 +313,7 @@ static void pnv_occ_register_types(void)
     type_register_static(&pnv_occ_type_info);
     type_register_static(&pnv_occ_power8_type_info);
     type_register_static(&pnv_occ_power9_type_info);
+    type_register_static(&pnv_occ_power10_type_info);
 }
 
 type_init(pnv_occ_register_types);
-- 
2.25.4



  parent reply	other threads:[~2020-05-13 15:14 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-13 15:11 [PATCH 0/9] ppc/pnv: Introduce the XIVE2 and PHB5 controllers for the POWER10 chip Cédric Le Goater
2020-05-13 15:11 ` [PATCH 1/9] ppc/xive: Export PQ get/set routines Cédric Le Goater
2020-05-13 15:11 ` [PATCH 2/9] ppc/xive: Export xive_presenter_notify() Cédric Le Goater
2020-05-19  9:18   ` Greg Kurz
2020-05-13 15:11 ` [PATCH 3/9] ppc/xive2: Introduce a XIVE2 core framework Cédric Le Goater
2020-05-20 16:40   ` Greg Kurz
2020-05-25 11:41     ` Cédric Le Goater
2020-05-13 15:11 ` [PATCH 4/9] ppc/xive2: Introduce a presenter matching routine Cédric Le Goater
2020-05-20 17:17   ` Greg Kurz
2020-05-25 12:11     ` Cédric Le Goater
2020-05-20 17:20   ` Greg Kurz
2020-05-13 15:11 ` [PATCH 5/9] ppc/pnv: Add a XIVE2 controller to the POWER10 chip Cédric Le Goater
2020-05-19  9:48   ` Greg Kurz
2020-05-25 10:12     ` Cédric Le Goater
2020-05-13 15:11 ` Cédric Le Goater [this message]
2020-05-20 14:22   ` [PATCH 6/9] ppc/pnv: Add a OCC model for POWER10 Greg Kurz
2020-05-25 11:14     ` Cédric Le Goater
2020-05-13 15:11 ` [PATCH 7/9] ppc/pnv: Add POWER10 quads Cédric Le Goater
2020-05-20 14:44   ` Greg Kurz
2020-05-25 11:27     ` Cédric Le Goater
2020-05-13 15:11 ` [PATCH 8/9] ppc/pnv: Add model for POWER9 PHB5 PCIe Host bridge Cédric Le Goater
2020-05-20 13:46   ` Greg Kurz
2020-05-25 10:13     ` Cédric Le Goater
2020-05-13 15:11 ` [PATCH 9/9] ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10) Cédric Le Goater
2020-05-19  9:40 ` [PATCH 0/9] ppc/pnv: Introduce the XIVE2 and PHB5 controllers for the POWER10 chip Greg Kurz

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200513151109.453530-7-clg@kaod.org \
    --to=clg@kaod.org \
    --cc=david@gibson.dropbear.id.au \
    --cc=groug@kaod.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).