Re: [PATCH 4/9] ppc/xive2: Introduce a presenter matching routine

["Cédric Le Goater" <clg@kaod.org>]

On 5/20/20 7:17 PM, Greg Kurz wrote:
> On Wed, 13 May 2020 17:11:04 +0200
> Cédric Le Goater <clg@kaod.org> wrote:
> 
>> The VP space is larger in XIVE2 (P10), 24 bits instead of 19bits on
>> XIVE (P9), and the CAM line can use a 7bits or 8bits thread id.
>>
>> For now, we only use 7bits thread ids, same as P9, but because of the
>> change of the size of the VP space, the CAM matching routine is
>> different between P9 and P10. It is easier to duplicate the whole
>> routine than to add extra handlers in xive_presenter_tctx_match() used
>> for P9.
>>
> 
> It's a bit of a pity to duplicate this routine. What about turning it
> into a helper with some extra arguments and come up with dedicated
> users for P9 and P10 ?

The size of the context fields have changed. It's not sure it will
be better.

>> We might come with a better solution later on, after we have added
>> some more support for the XIVE2 controller.
>>
> 
> Of course if you envision substantial changes that would prevent to share
> enough logic, you can ignore the previous comment. The duplicated routine
> looks fine.
> 
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>>  include/hw/ppc/xive2.h |  9 +++++
>>  hw/intc/xive2.c        | 87 ++++++++++++++++++++++++++++++++++++++++++
>>  2 files changed, 96 insertions(+)
>>
>> diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
>> index cb15487efdb6..4aefca4d96f1 100644
>> --- a/include/hw/ppc/xive2.h
>> +++ b/include/hw/ppc/xive2.h
>> @@ -60,6 +60,15 @@ int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
>>  
>>  void xive2_router_notify(XiveNotifier *xn, uint32_t lisn);
>>  
>> +/*
>> + * XIVE2 Presenter (POWER10)
>> + */
>> +
>> +int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
>> +                                uint8_t format,
>> +                                uint8_t nvt_blk, uint32_t nvt_idx,
>> +                                bool cam_ignore, uint32_t logic_serv);
>> +
>>  /*
>>   * XIVE2 END ESBs  (POWER10)
>>   */
>> diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
>> index 15ea04cf1822..1ce9d995e990 100644
>> --- a/hw/intc/xive2.c
>> +++ b/hw/intc/xive2.c
>> @@ -20,6 +20,11 @@
>>  #include "hw/ppc/xive2.h"
>>  #include "hw/ppc/xive2_regs.h"
>>  
>> +static inline uint32_t xive_tctx_word2(uint8_t *ring)
>> +{
>> +    return *((uint32_t *) &ring[TM_WORD2]);
>> +}
>> +
>>  static uint8_t priority_to_ipb(uint8_t priority)
>>  {
>>      return priority > XIVE_PRIORITY_MAX ?
>> @@ -212,6 +217,88 @@ static int xive2_router_get_block_id(Xive2Router *xrtr)
>>     return xrc->get_block_id(xrtr);
>>  }
>>  
>> +/*
>> + * Encode the HW CAM line with 7bit or 8bit thread id. The thread id
>> + * width and block id width is configurable at the IC level.
>> + *
>> + *    chipid << 19 | 0000000 0 0001 threadid (7Bit)
>> + *    chipid << 24 | 0000 0000 0000 0001 threadid (8Bit)
>> + */
> 
> What about introducing:
> 
> #define XIVE2_PIR_TO_NVP_IDX(pir, width) \
>     (1 << (width) | ((pir) & ((1 << (width)) - 1))
> 
> or any better name you can think of and...

yes. This looks nice.

Thanks,

C. 

> 
>> +static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx)
>> +{
>> +    Xive2Router *xrtr = XIVE2_ROUTER(xptr);
>> +    CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
>> +    uint32_t pir = env->spr_cb[SPR_PIR].default_value;
>> +    uint8_t blk = xive2_router_get_block_id(xrtr);
>> +    uint8_t tid_shift = 7;
>> +    uint8_t tid_mask = (1 << tid_shift) - 1;
>> +
>> +    return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask));
> 
> ... turn this into:
> 
>     /* We only use 7bit thread ids for now */
>     return xive2_nvp_cam_line(blk, XIVE2_PIR_TO_NVP_IDX(pir, 7));
> 
>> +}
>> +
>> +/*
>> + * The thread context register words are in big-endian format.
>> + */
>> +int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
>> +                                uint8_t format,
>> +                                uint8_t nvt_blk, uint32_t nvt_idx,
>> +                                bool cam_ignore, uint32_t logic_serv)
>> +{
>> +    uint32_t cam =   xive2_nvp_cam_line(nvt_blk, nvt_idx);
>> +    uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]);
>> +    uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);
>> +    uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
>> +    uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]);
>> +
>> +    /*
>> +     * TODO (PowerNV): ignore mode. The low order bits of the NVT
>> +     * identifier are ignored in the "CAM" match.
>> +     */
>> +
>> +    if (format == 0) {
>> +        if (cam_ignore == true) {
>> +            /*
>> +             * F=0 & i=1: Logical server notification (bits ignored at
>> +             * the end of the NVT identifier)
>> +             */
>> +            qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n",
>> +                          nvt_blk, nvt_idx);
>> +             return -1;
>> +        }
>> +
>> +        /* F=0 & i=0: Specific NVT notification */
>> +
>> +        /* PHYS ring */
>> +        if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) &&
>> +            cam == xive2_tctx_hw_cam_line(xptr, tctx)) {
>> +            return TM_QW3_HV_PHYS;
>> +        }
>> +
>> +        /* HV POOL ring */
>> +        if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) &&
>> +            cam == xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2)) {
>> +            return TM_QW2_HV_POOL;
>> +        }
>> +
>> +        /* OS ring */
>> +        if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) &&
>> +            cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) {
>> +            return TM_QW1_OS;
>> +        }
>> +    } else {
>> +        /* F=1 : User level Event-Based Branch (EBB) notification */
>> +
>> +        /* USER ring */
>> +        if  ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) &&
>> +             (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) &&
>> +             (be32_to_cpu(qw0w2) & TM2_QW0W2_VU) &&
>> +             (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) {
>> +            return TM_QW0_USER;
>> +        }
>> +    }
>> +    return -1;
>> +}
>> +
>>  static void xive2_router_realize(DeviceState *dev, Error **errp)
>>  {
>>      Xive2Router *xrtr = XIVE2_ROUTER(dev);
>