From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: richard.henderson@linaro.org, wxy194768@alibaba-inc.com,
wenmeng_zhang@c-sky.com, alistair.francis@wdc.com,
palmer@dabbelt.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v8 20/62] target/riscv: vector widening integer multiply instructions
Date: Thu, 21 May 2020 17:43:31 +0800 [thread overview]
Message-ID: <20200521094413.10425-21-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200521094413.10425-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 19 +++++++++
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++++
target/riscv/vector_helper.c | 51 +++++++++++++++++++++++++
4 files changed, 84 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 5fd718771c..e5c3a66903 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -595,3 +595,22 @@ DEF_HELPER_6(vrem_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrem_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrem_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrem_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vwmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwmulu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwmulu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwmulu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwmulsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwmulsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwmulsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwmul_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwmul_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwmul_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwmulu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwmulu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwmulu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwmulsu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwmulsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vwmulsu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 7fb8f8fad8..ae7cfa3e28 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -379,6 +379,12 @@ vremu_vv 100010 . ..... ..... 010 ..... 1010111 @r_vm
vremu_vx 100010 . ..... ..... 110 ..... 1010111 @r_vm
vrem_vv 100011 . ..... ..... 010 ..... 1010111 @r_vm
vrem_vx 100011 . ..... ..... 110 ..... 1010111 @r_vm
+vwmulu_vv 111000 . ..... ..... 010 ..... 1010111 @r_vm
+vwmulu_vx 111000 . ..... ..... 110 ..... 1010111 @r_vm
+vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm
+vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm
+vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm
+vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index df89ddc767..cd28c135b8 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1591,3 +1591,11 @@ GEN_OPIVX_TRANS(vdivu_vx, opivx_check)
GEN_OPIVX_TRANS(vdiv_vx, opivx_check)
GEN_OPIVX_TRANS(vremu_vx, opivx_check)
GEN_OPIVX_TRANS(vrem_vx, opivx_check)
+
+/* Vector Widening Integer Multiply Instructions */
+GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check)
+GEN_OPIVX_WIDEN_TRANS(vwmul_vx)
+GEN_OPIVX_WIDEN_TRANS(vwmulu_vx)
+GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 07d2d57c9d..0af2acb8ad 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -862,6 +862,18 @@ GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl)
#define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t
#define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t
#define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t
+#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
+#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
+#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
+#define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t
+#define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t
+#define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t
+#define WOP_SUS_B int16_t, uint8_t, int8_t, uint16_t, int16_t
+#define WOP_SUS_H int32_t, uint16_t, int16_t, uint32_t, int32_t
+#define WOP_SUS_W int64_t, uint32_t, int32_t, uint64_t, int64_t
+#define WOP_SSU_B int16_t, int8_t, uint8_t, int16_t, uint16_t
+#define WOP_SSU_H int32_t, int16_t, uint16_t, int32_t, uint32_t
+#define WOP_SSU_W int64_t, int32_t, uint32_t, int64_t, uint64_t
/* operation of two vector elements */
typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
@@ -1839,3 +1851,42 @@ GEN_VEXT_VX(vrem_vx_b, 1, 1, clearb)
GEN_VEXT_VX(vrem_vx_h, 2, 2, clearh)
GEN_VEXT_VX(vrem_vx_w, 4, 4, clearl)
GEN_VEXT_VX(vrem_vx_d, 8, 8, clearq)
+
+/* Vector Widening Integer Multiply Instructions */
+RVVCALL(OPIVV2, vwmul_vv_b, WOP_SSS_B, H2, H1, H1, DO_MUL)
+RVVCALL(OPIVV2, vwmul_vv_h, WOP_SSS_H, H4, H2, H2, DO_MUL)
+RVVCALL(OPIVV2, vwmul_vv_w, WOP_SSS_W, H8, H4, H4, DO_MUL)
+RVVCALL(OPIVV2, vwmulu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MUL)
+RVVCALL(OPIVV2, vwmulu_vv_h, WOP_UUU_H, H4, H2, H2, DO_MUL)
+RVVCALL(OPIVV2, vwmulu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MUL)
+RVVCALL(OPIVV2, vwmulsu_vv_b, WOP_SUS_B, H2, H1, H1, DO_MUL)
+RVVCALL(OPIVV2, vwmulsu_vv_h, WOP_SUS_H, H4, H2, H2, DO_MUL)
+RVVCALL(OPIVV2, vwmulsu_vv_w, WOP_SUS_W, H8, H4, H4, DO_MUL)
+GEN_VEXT_VV(vwmul_vv_b, 1, 2, clearh)
+GEN_VEXT_VV(vwmul_vv_h, 2, 4, clearl)
+GEN_VEXT_VV(vwmul_vv_w, 4, 8, clearq)
+GEN_VEXT_VV(vwmulu_vv_b, 1, 2, clearh)
+GEN_VEXT_VV(vwmulu_vv_h, 2, 4, clearl)
+GEN_VEXT_VV(vwmulu_vv_w, 4, 8, clearq)
+GEN_VEXT_VV(vwmulsu_vv_b, 1, 2, clearh)
+GEN_VEXT_VV(vwmulsu_vv_h, 2, 4, clearl)
+GEN_VEXT_VV(vwmulsu_vv_w, 4, 8, clearq)
+
+RVVCALL(OPIVX2, vwmul_vx_b, WOP_SSS_B, H2, H1, DO_MUL)
+RVVCALL(OPIVX2, vwmul_vx_h, WOP_SSS_H, H4, H2, DO_MUL)
+RVVCALL(OPIVX2, vwmul_vx_w, WOP_SSS_W, H8, H4, DO_MUL)
+RVVCALL(OPIVX2, vwmulu_vx_b, WOP_UUU_B, H2, H1, DO_MUL)
+RVVCALL(OPIVX2, vwmulu_vx_h, WOP_UUU_H, H4, H2, DO_MUL)
+RVVCALL(OPIVX2, vwmulu_vx_w, WOP_UUU_W, H8, H4, DO_MUL)
+RVVCALL(OPIVX2, vwmulsu_vx_b, WOP_SUS_B, H2, H1, DO_MUL)
+RVVCALL(OPIVX2, vwmulsu_vx_h, WOP_SUS_H, H4, H2, DO_MUL)
+RVVCALL(OPIVX2, vwmulsu_vx_w, WOP_SUS_W, H8, H4, DO_MUL)
+GEN_VEXT_VX(vwmul_vx_b, 1, 2, clearh)
+GEN_VEXT_VX(vwmul_vx_h, 2, 4, clearl)
+GEN_VEXT_VX(vwmul_vx_w, 4, 8, clearq)
+GEN_VEXT_VX(vwmulu_vx_b, 1, 2, clearh)
+GEN_VEXT_VX(vwmulu_vx_h, 2, 4, clearl)
+GEN_VEXT_VX(vwmulu_vx_w, 4, 8, clearq)
+GEN_VEXT_VX(vwmulsu_vx_b, 1, 2, clearh)
+GEN_VEXT_VX(vwmulsu_vx_h, 2, 4, clearl)
+GEN_VEXT_VX(vwmulsu_vx_w, 4, 8, clearq)
--
2.23.0
next prev parent reply other threads:[~2020-05-21 10:25 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-21 9:43 [PATCH v8 00/62] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 01/62] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 02/62] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 03/62] target/riscv: support vector extension csr LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 04/62] target/riscv: add vector configure instruction LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 05/62] target/riscv: add an internals.h header LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 06/62] target/riscv: add vector stride load and store instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 07/62] target/riscv: add vector index " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 08/62] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 09/62] target/riscv: add vector amo operations LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 10/62] target/riscv: vector single-width integer add and subtract LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 11/62] target/riscv: vector widening " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 12/62] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 13/62] target/riscv: vector bitwise logical instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 14/62] target/riscv: vector single-width bit shift instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 15/62] target/riscv: vector narrowing integer right " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 16/62] target/riscv: vector integer comparison instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 17/62] target/riscv: vector integer min/max instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 18/62] target/riscv: vector single-width integer multiply instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 19/62] target/riscv: vector integer divide instructions LIU Zhiwei
2020-05-21 9:43 ` LIU Zhiwei [this message]
2020-05-21 9:43 ` [PATCH v8 21/62] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 22/62] target/riscv: vector widening " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 23/62] target/riscv: vector integer merge and move instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 24/62] target/riscv: vector single-width saturating add and subtract LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 25/62] target/riscv: vector single-width averaging " LIU Zhiwei
2020-06-04 20:22 ` Richard Henderson
2020-05-21 9:43 ` [PATCH v8 26/62] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei
2020-06-04 20:26 ` Richard Henderson
2020-05-21 9:43 ` [PATCH v8 27/62] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 28/62] target/riscv: vector single-width scaling shift instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 29/62] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes LIU Zhiwei
2020-05-29 19:59 ` Alistair Francis
2020-06-03 4:27 ` Richard Henderson
2020-06-03 5:46 ` LIU Zhiwei
2020-06-04 20:15 ` Richard Henderson
2020-06-05 2:50 ` LIU Zhiwei
2020-06-05 3:30 ` Richard Henderson
2020-06-08 2:39 ` LIU Zhiwei
2020-06-08 16:28 ` Richard Henderson
2020-05-21 9:43 ` [PATCH v8 31/62] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 32/62] target/riscv: vector widening " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 33/62] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 34/62] target/riscv: vector widening floating-point multiply LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 35/62] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 36/62] target/riscv: vector widening " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 37/62] target/riscv: vector floating-point square-root instruction LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 38/62] target/riscv: vector floating-point min/max instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 39/62] target/riscv: vector floating-point sign-injection instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 40/62] target/riscv: vector floating-point compare instructions LIU Zhiwei
2020-06-04 20:51 ` Richard Henderson
2020-06-05 2:56 ` LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 41/62] target/riscv: vector floating-point classify instructions LIU Zhiwei
2020-05-29 20:20 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 42/62] target/riscv: vector floating-point merge instructions LIU Zhiwei
2020-05-29 20:36 ` Alistair Francis
2020-06-04 20:57 ` Richard Henderson
2020-05-21 9:43 ` [PATCH v8 43/62] target/riscv: vector floating-point/integer type-convert instructions LIU Zhiwei
2020-05-29 20:40 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 44/62] target/riscv: widening " LIU Zhiwei
2020-05-29 20:43 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 45/62] target/riscv: narrowing " LIU Zhiwei
2020-05-29 20:51 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 46/62] target/riscv: vector single-width integer reduction instructions LIU Zhiwei
2020-05-29 20:58 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 47/62] target/riscv: vector wideing " LIU Zhiwei
2020-05-29 20:59 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 48/62] target/riscv: vector single-width floating-point " LIU Zhiwei
2020-05-29 21:01 ` Alistair Francis
2020-05-21 9:44 ` [PATCH v8 49/62] target/riscv: vector widening " LIU Zhiwei
2020-05-29 21:03 ` Alistair Francis
2020-05-21 9:44 ` [PATCH v8 50/62] target/riscv: vector mask-register logical instructions LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 51/62] target/riscv: vector mask population count vmpopc LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 52/62] target/riscv: vmfirst find-first-set mask bit LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 53/62] target/riscv: set-X-first " LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 54/62] target/riscv: vector iota instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 55/62] target/riscv: vector element index instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 56/62] target/riscv: integer extract instruction LIU Zhiwei
2020-06-04 21:05 ` Richard Henderson
2020-05-21 9:44 ` [PATCH v8 57/62] target/riscv: integer scalar move instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 58/62] target/riscv: floating-point scalar move instructions LIU Zhiwei
2020-06-04 21:32 ` Richard Henderson
2020-06-05 2:53 ` LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 59/62] target/riscv: vector slide instructions LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 60/62] target/riscv: vector register gather instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 61/62] target/riscv: vector compress instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 62/62] target/riscv: configure and turn on vector extension from command line LIU Zhiwei
2020-05-21 13:12 ` [PATCH v8 00/62] target/riscv: support vector extension v0.7.1 no-reply
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