From: Alistair Francis <alistair23@gmail.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v8 49/62] target/riscv: vector widening floating-point reduction instructions
Date: Fri, 29 May 2020 14:03:26 -0700 [thread overview]
Message-ID: <CAKmqyKMK3O453p_S4zXehguW9VUTsxjd0jH_HwzhniR-cbPYhg@mail.gmail.com> (raw)
In-Reply-To: <20200521094413.10425-50-zhiwei_liu@c-sky.com>
On Thu, May 21, 2020 at 4:23 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/helper.h | 3 ++
> target/riscv/insn32.decode | 2 ++
> target/riscv/insn_trans/trans_rvv.inc.c | 3 ++
> target/riscv/vector_helper.c | 46 +++++++++++++++++++++++++
> 4 files changed, 54 insertions(+)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 17fd02c323..6b932b444d 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1083,3 +1083,6 @@ DEF_HELPER_6(vfredmax_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
> DEF_HELPER_6(vfredmin_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
> DEF_HELPER_6(vfredmin_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
> DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
> +
> +DEF_HELPER_6(vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 0592075167..526a964d28 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -543,6 +543,8 @@ vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm
> vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm
> vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
> vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
> +# Vector widening ordered and unordered float reduction sum
> +vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm
>
> vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
> vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
> index d74054ff04..31848a1f88 100644
> --- a/target/riscv/insn_trans/trans_rvv.inc.c
> +++ b/target/riscv/insn_trans/trans_rvv.inc.c
> @@ -2342,3 +2342,6 @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check)
> GEN_OPFVV_TRANS(vfredsum_vs, reduction_check)
> GEN_OPFVV_TRANS(vfredmax_vs, reduction_check)
> GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
> +
> +/* Vector Widening Floating-Point Reduction Instructions */
> +GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index f37b65288a..0074d12538 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4455,3 +4455,49 @@ GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum, clearq)
> GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum, clearh)
> GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum, clearl)
> GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum, clearq)
> +
> +/* Vector Widening Floating-Point Reduction Instructions */
> +/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
> +void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
> + void *vs2, CPURISCVState *env, uint32_t desc)
> +{
> + uint32_t mlen = vext_mlen(desc);
> + uint32_t vm = vext_vm(desc);
> + uint32_t vl = env->vl;
> + uint32_t i;
> + uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
> + uint32_t s1 = *((uint32_t *)vs1 + H4(0));
> +
> + for (i = 0; i < vl; i++) {
> + uint16_t s2 = *((uint16_t *)vs2 + H2(i));
> + if (!vm && !vext_elem_mask(v0, mlen, i)) {
> + continue;
> + }
> + s1 = float32_add(s1, float16_to_float32(s2, true, &env->fp_status),
> + &env->fp_status);
> + }
> + *((uint32_t *)vd + H4(0)) = s1;
> + clearl(vd, 1, sizeof(uint32_t), tot);
> +}
> +
> +void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
> + void *vs2, CPURISCVState *env, uint32_t desc)
> +{
> + uint32_t mlen = vext_mlen(desc);
> + uint32_t vm = vext_vm(desc);
> + uint32_t vl = env->vl;
> + uint32_t i;
> + uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
> + uint64_t s1 = *((uint64_t *)vs1);
> +
> + for (i = 0; i < vl; i++) {
> + uint32_t s2 = *((uint32_t *)vs2 + H4(i));
> + if (!vm && !vext_elem_mask(v0, mlen, i)) {
> + continue;
> + }
> + s1 = float64_add(s1, float32_to_float64(s2, &env->fp_status),
> + &env->fp_status);
> + }
> + *((uint64_t *)vd) = s1;
> + clearq(vd, 1, sizeof(uint64_t), tot);
> +}
> --
> 2.23.0
>
>
next prev parent reply other threads:[~2020-05-29 21:13 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-21 9:43 [PATCH v8 00/62] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 01/62] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 02/62] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 03/62] target/riscv: support vector extension csr LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 04/62] target/riscv: add vector configure instruction LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 05/62] target/riscv: add an internals.h header LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 06/62] target/riscv: add vector stride load and store instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 07/62] target/riscv: add vector index " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 08/62] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 09/62] target/riscv: add vector amo operations LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 10/62] target/riscv: vector single-width integer add and subtract LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 11/62] target/riscv: vector widening " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 12/62] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 13/62] target/riscv: vector bitwise logical instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 14/62] target/riscv: vector single-width bit shift instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 15/62] target/riscv: vector narrowing integer right " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 16/62] target/riscv: vector integer comparison instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 17/62] target/riscv: vector integer min/max instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 18/62] target/riscv: vector single-width integer multiply instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 19/62] target/riscv: vector integer divide instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 20/62] target/riscv: vector widening integer multiply instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 21/62] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 22/62] target/riscv: vector widening " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 23/62] target/riscv: vector integer merge and move instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 24/62] target/riscv: vector single-width saturating add and subtract LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 25/62] target/riscv: vector single-width averaging " LIU Zhiwei
2020-06-04 20:22 ` Richard Henderson
2020-05-21 9:43 ` [PATCH v8 26/62] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei
2020-06-04 20:26 ` Richard Henderson
2020-05-21 9:43 ` [PATCH v8 27/62] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 28/62] target/riscv: vector single-width scaling shift instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 29/62] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes LIU Zhiwei
2020-05-29 19:59 ` Alistair Francis
2020-06-03 4:27 ` Richard Henderson
2020-06-03 5:46 ` LIU Zhiwei
2020-06-04 20:15 ` Richard Henderson
2020-06-05 2:50 ` LIU Zhiwei
2020-06-05 3:30 ` Richard Henderson
2020-06-08 2:39 ` LIU Zhiwei
2020-06-08 16:28 ` Richard Henderson
2020-05-21 9:43 ` [PATCH v8 31/62] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 32/62] target/riscv: vector widening " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 33/62] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 34/62] target/riscv: vector widening floating-point multiply LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 35/62] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 36/62] target/riscv: vector widening " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 37/62] target/riscv: vector floating-point square-root instruction LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 38/62] target/riscv: vector floating-point min/max instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 39/62] target/riscv: vector floating-point sign-injection instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 40/62] target/riscv: vector floating-point compare instructions LIU Zhiwei
2020-06-04 20:51 ` Richard Henderson
2020-06-05 2:56 ` LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 41/62] target/riscv: vector floating-point classify instructions LIU Zhiwei
2020-05-29 20:20 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 42/62] target/riscv: vector floating-point merge instructions LIU Zhiwei
2020-05-29 20:36 ` Alistair Francis
2020-06-04 20:57 ` Richard Henderson
2020-05-21 9:43 ` [PATCH v8 43/62] target/riscv: vector floating-point/integer type-convert instructions LIU Zhiwei
2020-05-29 20:40 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 44/62] target/riscv: widening " LIU Zhiwei
2020-05-29 20:43 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 45/62] target/riscv: narrowing " LIU Zhiwei
2020-05-29 20:51 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 46/62] target/riscv: vector single-width integer reduction instructions LIU Zhiwei
2020-05-29 20:58 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 47/62] target/riscv: vector wideing " LIU Zhiwei
2020-05-29 20:59 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 48/62] target/riscv: vector single-width floating-point " LIU Zhiwei
2020-05-29 21:01 ` Alistair Francis
2020-05-21 9:44 ` [PATCH v8 49/62] target/riscv: vector widening " LIU Zhiwei
2020-05-29 21:03 ` Alistair Francis [this message]
2020-05-21 9:44 ` [PATCH v8 50/62] target/riscv: vector mask-register logical instructions LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 51/62] target/riscv: vector mask population count vmpopc LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 52/62] target/riscv: vmfirst find-first-set mask bit LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 53/62] target/riscv: set-X-first " LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 54/62] target/riscv: vector iota instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 55/62] target/riscv: vector element index instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 56/62] target/riscv: integer extract instruction LIU Zhiwei
2020-06-04 21:05 ` Richard Henderson
2020-05-21 9:44 ` [PATCH v8 57/62] target/riscv: integer scalar move instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 58/62] target/riscv: floating-point scalar move instructions LIU Zhiwei
2020-06-04 21:32 ` Richard Henderson
2020-06-05 2:53 ` LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 59/62] target/riscv: vector slide instructions LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 60/62] target/riscv: vector register gather instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 61/62] target/riscv: vector compress instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 62/62] target/riscv: configure and turn on vector extension from command line LIU Zhiwei
2020-05-21 13:12 ` [PATCH v8 00/62] target/riscv: support vector extension v0.7.1 no-reply
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