From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: richard.henderson@linaro.org, wxy194768@alibaba-inc.com,
wenmeng_zhang@c-sky.com, alistair.francis@wdc.com,
palmer@dabbelt.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v8 57/62] target/riscv: integer scalar move instruction
Date: Thu, 21 May 2020 17:44:08 +0800 [thread overview]
Message-ID: <20200521094413.10425-58-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200521094413.10425-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 60 +++++++++++++++++++++++++
target/riscv/internals.h | 6 +++
3 files changed, 67 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 26dd0f1b1b..0741a25540 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -562,6 +562,7 @@ vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
+vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 1c348f1e1e..27ae87e7b3 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2640,3 +2640,63 @@ static bool trans_vext_x_v(DisasContext *s, arg_r *a)
tcg_temp_free_i64(tmp);
return true;
}
+
+/* Integer Scalar Move Instruction */
+
+static void store_element(TCGv_i64 val, TCGv_ptr base,
+ int ofs, int sew)
+{
+ switch (sew) {
+ case MO_8:
+ tcg_gen_st8_i64(val, base, ofs);
+ break;
+ case MO_16:
+ tcg_gen_st16_i64(val, base, ofs);
+ break;
+ case MO_32:
+ tcg_gen_st32_i64(val, base, ofs);
+ break;
+ case MO_64:
+ tcg_gen_st_i64(val, base, ofs);
+ break;
+ default:
+ g_assert_not_reached();
+ break;
+ }
+}
+
+/*
+ * Store vreg[idx] = val.
+ * The index must be in range of VLMAX.
+ */
+static void vec_element_storei(DisasContext *s, int vreg,
+ int idx, TCGv_i64 val)
+{
+ store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew);
+}
+
+/* vmv.s.x vd, rs1 # vd[0] = rs1 */
+static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
+{
+ if (vext_check_isa_ill(s)) {
+ /* This instruction ignores LMUL and vector register groups */
+ int maxsz = s->vlen >> 3;
+ TCGv_i64 t1;
+ TCGLabel *over = gen_new_label();
+
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0);
+ if (a->rs1 == 0) {
+ goto done;
+ }
+
+ t1 = tcg_temp_new_i64();
+ tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
+ vec_element_storei(s, a->rd, 0, t1);
+ tcg_temp_free_i64(t1);
+ done:
+ gen_set_label(over);
+ return true;
+ }
+ return false;
+}
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index ed2ad7f0f1..96438ac56c 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -35,4 +35,10 @@ bool riscv_cpu_set_rounding_mode(CPURISCVState *env, uint32_t rm);
target_ulong fclass_h(uint64_t frs1);
target_ulong fclass_s(uint64_t frs1);
target_ulong fclass_d(uint64_t frs1);
+
+#define SEW8 0
+#define SEW16 1
+#define SEW32 2
+#define SEW64 3
+
#endif
--
2.23.0
next prev parent reply other threads:[~2020-05-21 11:40 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-21 9:43 [PATCH v8 00/62] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 01/62] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 02/62] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 03/62] target/riscv: support vector extension csr LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 04/62] target/riscv: add vector configure instruction LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 05/62] target/riscv: add an internals.h header LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 06/62] target/riscv: add vector stride load and store instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 07/62] target/riscv: add vector index " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 08/62] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 09/62] target/riscv: add vector amo operations LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 10/62] target/riscv: vector single-width integer add and subtract LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 11/62] target/riscv: vector widening " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 12/62] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 13/62] target/riscv: vector bitwise logical instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 14/62] target/riscv: vector single-width bit shift instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 15/62] target/riscv: vector narrowing integer right " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 16/62] target/riscv: vector integer comparison instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 17/62] target/riscv: vector integer min/max instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 18/62] target/riscv: vector single-width integer multiply instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 19/62] target/riscv: vector integer divide instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 20/62] target/riscv: vector widening integer multiply instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 21/62] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 22/62] target/riscv: vector widening " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 23/62] target/riscv: vector integer merge and move instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 24/62] target/riscv: vector single-width saturating add and subtract LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 25/62] target/riscv: vector single-width averaging " LIU Zhiwei
2020-06-04 20:22 ` Richard Henderson
2020-05-21 9:43 ` [PATCH v8 26/62] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei
2020-06-04 20:26 ` Richard Henderson
2020-05-21 9:43 ` [PATCH v8 27/62] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 28/62] target/riscv: vector single-width scaling shift instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 29/62] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes LIU Zhiwei
2020-05-29 19:59 ` Alistair Francis
2020-06-03 4:27 ` Richard Henderson
2020-06-03 5:46 ` LIU Zhiwei
2020-06-04 20:15 ` Richard Henderson
2020-06-05 2:50 ` LIU Zhiwei
2020-06-05 3:30 ` Richard Henderson
2020-06-08 2:39 ` LIU Zhiwei
2020-06-08 16:28 ` Richard Henderson
2020-05-21 9:43 ` [PATCH v8 31/62] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 32/62] target/riscv: vector widening " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 33/62] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 34/62] target/riscv: vector widening floating-point multiply LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 35/62] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 36/62] target/riscv: vector widening " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 37/62] target/riscv: vector floating-point square-root instruction LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 38/62] target/riscv: vector floating-point min/max instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 39/62] target/riscv: vector floating-point sign-injection instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 40/62] target/riscv: vector floating-point compare instructions LIU Zhiwei
2020-06-04 20:51 ` Richard Henderson
2020-06-05 2:56 ` LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 41/62] target/riscv: vector floating-point classify instructions LIU Zhiwei
2020-05-29 20:20 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 42/62] target/riscv: vector floating-point merge instructions LIU Zhiwei
2020-05-29 20:36 ` Alistair Francis
2020-06-04 20:57 ` Richard Henderson
2020-05-21 9:43 ` [PATCH v8 43/62] target/riscv: vector floating-point/integer type-convert instructions LIU Zhiwei
2020-05-29 20:40 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 44/62] target/riscv: widening " LIU Zhiwei
2020-05-29 20:43 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 45/62] target/riscv: narrowing " LIU Zhiwei
2020-05-29 20:51 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 46/62] target/riscv: vector single-width integer reduction instructions LIU Zhiwei
2020-05-29 20:58 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 47/62] target/riscv: vector wideing " LIU Zhiwei
2020-05-29 20:59 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 48/62] target/riscv: vector single-width floating-point " LIU Zhiwei
2020-05-29 21:01 ` Alistair Francis
2020-05-21 9:44 ` [PATCH v8 49/62] target/riscv: vector widening " LIU Zhiwei
2020-05-29 21:03 ` Alistair Francis
2020-05-21 9:44 ` [PATCH v8 50/62] target/riscv: vector mask-register logical instructions LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 51/62] target/riscv: vector mask population count vmpopc LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 52/62] target/riscv: vmfirst find-first-set mask bit LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 53/62] target/riscv: set-X-first " LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 54/62] target/riscv: vector iota instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 55/62] target/riscv: vector element index instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 56/62] target/riscv: integer extract instruction LIU Zhiwei
2020-06-04 21:05 ` Richard Henderson
2020-05-21 9:44 ` LIU Zhiwei [this message]
2020-05-21 9:44 ` [PATCH v8 58/62] target/riscv: floating-point scalar move instructions LIU Zhiwei
2020-06-04 21:32 ` Richard Henderson
2020-06-05 2:53 ` LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 59/62] target/riscv: vector slide instructions LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 60/62] target/riscv: vector register gather instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 61/62] target/riscv: vector compress instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 62/62] target/riscv: configure and turn on vector extension from command line LIU Zhiwei
2020-05-21 13:12 ` [PATCH v8 00/62] target/riscv: support vector extension v0.7.1 no-reply
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