From: Alistair Francis <alistair23@gmail.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v8 41/62] target/riscv: vector floating-point classify instructions
Date: Fri, 29 May 2020 13:20:21 -0700 [thread overview]
Message-ID: <CAKmqyKOvhYwCrtyezCFXR8o3n2CRWoBYT_QDdRrn21tnSwx24g@mail.gmail.com> (raw)
In-Reply-To: <20200521094413.10425-42-zhiwei_liu@c-sky.com>
On Thu, May 21, 2020 at 4:07 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/fpu_helper.c | 33 +--------
> target/riscv/helper.h | 4 ++
> target/riscv/insn32.decode | 1 +
> target/riscv/insn_trans/trans_rvv.inc.c | 3 +
> target/riscv/internals.h | 5 ++
> target/riscv/vector_helper.c | 91 +++++++++++++++++++++++++
> 6 files changed, 107 insertions(+), 30 deletions(-)
>
> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
> index 262610e837..fdbdffaef2 100644
> --- a/target/riscv/fpu_helper.c
> +++ b/target/riscv/fpu_helper.c
> @@ -22,6 +22,7 @@
> #include "exec/exec-all.h"
> #include "exec/helper-proto.h"
> #include "fpu/softfloat.h"
> +#include "internals.h"
>
> target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
> {
> @@ -239,21 +240,7 @@ uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
>
> target_ulong helper_fclass_s(uint64_t frs1)
> {
> - float32 f = frs1;
> - bool sign = float32_is_neg(f);
> -
> - if (float32_is_infinity(f)) {
> - return sign ? 1 << 0 : 1 << 7;
> - } else if (float32_is_zero(f)) {
> - return sign ? 1 << 3 : 1 << 4;
> - } else if (float32_is_zero_or_denormal(f)) {
> - return sign ? 1 << 2 : 1 << 5;
> - } else if (float32_is_any_nan(f)) {
> - float_status s = { }; /* for snan_bit_is_one */
> - return float32_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
> - } else {
> - return sign ? 1 << 1 : 1 << 6;
> - }
> + return fclass_s(frs1);
> }
>
> uint64_t helper_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
> @@ -362,19 +349,5 @@ uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
>
> target_ulong helper_fclass_d(uint64_t frs1)
> {
> - float64 f = frs1;
> - bool sign = float64_is_neg(f);
> -
> - if (float64_is_infinity(f)) {
> - return sign ? 1 << 0 : 1 << 7;
> - } else if (float64_is_zero(f)) {
> - return sign ? 1 << 3 : 1 << 4;
> - } else if (float64_is_zero_or_denormal(f)) {
> - return sign ? 1 << 2 : 1 << 5;
> - } else if (float64_is_any_nan(f)) {
> - float_status s = { }; /* for snan_bit_is_one */
> - return float64_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
> - } else {
> - return sign ? 1 << 1 : 1 << 6;
> - }
> + return fclass_d(frs1);
> }
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index bedd4d0114..23b268df90 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -990,3 +990,7 @@ DEF_HELPER_6(vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
> DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32)
> DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32)
> DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32)
> +
> +DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_5(vfclass_v_d, void, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index b0f1c54d53..23e80fe954 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -512,6 +512,7 @@ vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
> vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
> vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm
> vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
> +vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm
>
> vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
> vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
> index 4a45c00ffb..621220e5ff 100644
> --- a/target/riscv/insn_trans/trans_rvv.inc.c
> +++ b/target/riscv/insn_trans/trans_rvv.inc.c
> @@ -2174,3 +2174,6 @@ GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check)
> GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
> GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
> GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
> +
> +/* Vector Floating-Point Classify Instruction */
> +GEN_OPFV_TRANS(vfclass_v, opfv_check)
> diff --git a/target/riscv/internals.h b/target/riscv/internals.h
> index 52f6af2513..ed2ad7f0f1 100644
> --- a/target/riscv/internals.h
> +++ b/target/riscv/internals.h
> @@ -30,4 +30,9 @@ FIELD(VDATA, WD, 11, 1)
>
> /* set float rounding mode */
> bool riscv_cpu_set_rounding_mode(CPURISCVState *env, uint32_t rm);
> +
> +/* float point classify helpers */
> +target_ulong fclass_h(uint64_t frs1);
> +target_ulong fclass_s(uint64_t frs1);
> +target_ulong fclass_d(uint64_t frs1);
> #endif
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 92227228b7..63d8873c0a 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4102,3 +4102,94 @@ GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet)
> GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet)
> GEN_VEXT_CMP_VF(vmford_vf_w, uint32_t, H4, !float32_unordered_quiet)
> GEN_VEXT_CMP_VF(vmford_vf_d, uint64_t, H8, !float64_unordered_quiet)
> +
> +/* Vector Floating-Point Classify Instruction */
> +#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
> +static void do_##NAME(void *vd, void *vs2, int i) \
> +{ \
> + TX2 s2 = *((T2 *)vs2 + HS2(i)); \
> + *((TD *)vd + HD(i)) = OP(s2); \
> +}
> +
> +#define GEN_VEXT_V(NAME, ESZ, DSZ, CLEAR_FN) \
> +void HELPER(NAME)(void *vd, void *v0, void *vs2, \
> + CPURISCVState *env, uint32_t desc) \
> +{ \
> + uint32_t vlmax = vext_maxsz(desc) / ESZ; \
> + uint32_t mlen = vext_mlen(desc); \
> + uint32_t vm = vext_vm(desc); \
> + uint32_t vl = env->vl; \
> + uint32_t i; \
> + \
> + for (i = 0; i < vl; i++) { \
> + if (!vm && !vext_elem_mask(v0, mlen, i)) { \
> + continue; \
> + } \
> + do_##NAME(vd, vs2, i); \
> + } \
> + CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
> +}
> +
> +target_ulong fclass_h(uint64_t frs1)
> +{
> + float16 f = frs1;
> + bool sign = float16_is_neg(f);
> +
> + if (float16_is_infinity(f)) {
> + return sign ? 1 << 0 : 1 << 7;
> + } else if (float16_is_zero(f)) {
> + return sign ? 1 << 3 : 1 << 4;
> + } else if (float16_is_zero_or_denormal(f)) {
> + return sign ? 1 << 2 : 1 << 5;
> + } else if (float16_is_any_nan(f)) {
> + float_status s = { }; /* for snan_bit_is_one */
> + return float16_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
> + } else {
> + return sign ? 1 << 1 : 1 << 6;
> + }
> +}
> +
> +target_ulong fclass_s(uint64_t frs1)
> +{
> + float32 f = frs1;
> + bool sign = float32_is_neg(f);
> +
> + if (float32_is_infinity(f)) {
> + return sign ? 1 << 0 : 1 << 7;
> + } else if (float32_is_zero(f)) {
> + return sign ? 1 << 3 : 1 << 4;
> + } else if (float32_is_zero_or_denormal(f)) {
> + return sign ? 1 << 2 : 1 << 5;
> + } else if (float32_is_any_nan(f)) {
> + float_status s = { }; /* for snan_bit_is_one */
> + return float32_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
> + } else {
> + return sign ? 1 << 1 : 1 << 6;
> + }
> +}
> +
> +target_ulong fclass_d(uint64_t frs1)
> +{
> + float64 f = frs1;
> + bool sign = float64_is_neg(f);
> +
> + if (float64_is_infinity(f)) {
> + return sign ? 1 << 0 : 1 << 7;
> + } else if (float64_is_zero(f)) {
> + return sign ? 1 << 3 : 1 << 4;
> + } else if (float64_is_zero_or_denormal(f)) {
> + return sign ? 1 << 2 : 1 << 5;
> + } else if (float64_is_any_nan(f)) {
> + float_status s = { }; /* for snan_bit_is_one */
> + return float64_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
> + } else {
> + return sign ? 1 << 1 : 1 << 6;
> + }
> +}
> +
> +RVVCALL(OPIVV1, vfclass_v_h, OP_UU_H, H2, H2, fclass_h)
> +RVVCALL(OPIVV1, vfclass_v_w, OP_UU_W, H4, H4, fclass_s)
> +RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d)
> +GEN_VEXT_V(vfclass_v_h, 2, 2, clearh)
> +GEN_VEXT_V(vfclass_v_w, 4, 4, clearl)
> +GEN_VEXT_V(vfclass_v_d, 8, 8, clearq)
> --
> 2.23.0
>
>
next prev parent reply other threads:[~2020-05-29 20:31 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-21 9:43 [PATCH v8 00/62] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 01/62] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 02/62] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 03/62] target/riscv: support vector extension csr LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 04/62] target/riscv: add vector configure instruction LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 05/62] target/riscv: add an internals.h header LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 06/62] target/riscv: add vector stride load and store instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 07/62] target/riscv: add vector index " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 08/62] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 09/62] target/riscv: add vector amo operations LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 10/62] target/riscv: vector single-width integer add and subtract LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 11/62] target/riscv: vector widening " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 12/62] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 13/62] target/riscv: vector bitwise logical instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 14/62] target/riscv: vector single-width bit shift instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 15/62] target/riscv: vector narrowing integer right " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 16/62] target/riscv: vector integer comparison instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 17/62] target/riscv: vector integer min/max instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 18/62] target/riscv: vector single-width integer multiply instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 19/62] target/riscv: vector integer divide instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 20/62] target/riscv: vector widening integer multiply instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 21/62] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 22/62] target/riscv: vector widening " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 23/62] target/riscv: vector integer merge and move instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 24/62] target/riscv: vector single-width saturating add and subtract LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 25/62] target/riscv: vector single-width averaging " LIU Zhiwei
2020-06-04 20:22 ` Richard Henderson
2020-05-21 9:43 ` [PATCH v8 26/62] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei
2020-06-04 20:26 ` Richard Henderson
2020-05-21 9:43 ` [PATCH v8 27/62] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 28/62] target/riscv: vector single-width scaling shift instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 29/62] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 30/62] target/riscv: Update fp_status when float rounding mode changes LIU Zhiwei
2020-05-29 19:59 ` Alistair Francis
2020-06-03 4:27 ` Richard Henderson
2020-06-03 5:46 ` LIU Zhiwei
2020-06-04 20:15 ` Richard Henderson
2020-06-05 2:50 ` LIU Zhiwei
2020-06-05 3:30 ` Richard Henderson
2020-06-08 2:39 ` LIU Zhiwei
2020-06-08 16:28 ` Richard Henderson
2020-05-21 9:43 ` [PATCH v8 31/62] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 32/62] target/riscv: vector widening " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 33/62] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 34/62] target/riscv: vector widening floating-point multiply LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 35/62] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 36/62] target/riscv: vector widening " LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 37/62] target/riscv: vector floating-point square-root instruction LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 38/62] target/riscv: vector floating-point min/max instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 39/62] target/riscv: vector floating-point sign-injection instructions LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 40/62] target/riscv: vector floating-point compare instructions LIU Zhiwei
2020-06-04 20:51 ` Richard Henderson
2020-06-05 2:56 ` LIU Zhiwei
2020-05-21 9:43 ` [PATCH v8 41/62] target/riscv: vector floating-point classify instructions LIU Zhiwei
2020-05-29 20:20 ` Alistair Francis [this message]
2020-05-21 9:43 ` [PATCH v8 42/62] target/riscv: vector floating-point merge instructions LIU Zhiwei
2020-05-29 20:36 ` Alistair Francis
2020-06-04 20:57 ` Richard Henderson
2020-05-21 9:43 ` [PATCH v8 43/62] target/riscv: vector floating-point/integer type-convert instructions LIU Zhiwei
2020-05-29 20:40 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 44/62] target/riscv: widening " LIU Zhiwei
2020-05-29 20:43 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 45/62] target/riscv: narrowing " LIU Zhiwei
2020-05-29 20:51 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 46/62] target/riscv: vector single-width integer reduction instructions LIU Zhiwei
2020-05-29 20:58 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 47/62] target/riscv: vector wideing " LIU Zhiwei
2020-05-29 20:59 ` Alistair Francis
2020-05-21 9:43 ` [PATCH v8 48/62] target/riscv: vector single-width floating-point " LIU Zhiwei
2020-05-29 21:01 ` Alistair Francis
2020-05-21 9:44 ` [PATCH v8 49/62] target/riscv: vector widening " LIU Zhiwei
2020-05-29 21:03 ` Alistair Francis
2020-05-21 9:44 ` [PATCH v8 50/62] target/riscv: vector mask-register logical instructions LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 51/62] target/riscv: vector mask population count vmpopc LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 52/62] target/riscv: vmfirst find-first-set mask bit LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 53/62] target/riscv: set-X-first " LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 54/62] target/riscv: vector iota instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 55/62] target/riscv: vector element index instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 56/62] target/riscv: integer extract instruction LIU Zhiwei
2020-06-04 21:05 ` Richard Henderson
2020-05-21 9:44 ` [PATCH v8 57/62] target/riscv: integer scalar move instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 58/62] target/riscv: floating-point scalar move instructions LIU Zhiwei
2020-06-04 21:32 ` Richard Henderson
2020-06-05 2:53 ` LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 59/62] target/riscv: vector slide instructions LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 60/62] target/riscv: vector register gather instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 61/62] target/riscv: vector compress instruction LIU Zhiwei
2020-05-21 9:44 ` [PATCH v8 62/62] target/riscv: configure and turn on vector extension from command line LIU Zhiwei
2020-05-21 13:12 ` [PATCH v8 00/62] target/riscv: support vector extension v0.7.1 no-reply
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