From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [PATCH 14/20] target/arm: Generalize inl_qrdmlah_* helper functions
Date: Fri, 14 Aug 2020 18:31:39 -0700 [thread overview]
Message-ID: <20200815013145.539409-15-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200815013145.539409-1-richard.henderson@linaro.org>
Unify add/sub helpers and add a parameter for rounding.
This will allow saturating non-rounding to reuse this code.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/vec_helper.c | 80 +++++++++++++++--------------------------
1 file changed, 29 insertions(+), 51 deletions(-)
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index 7d76412ee0..bbd1141dfc 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -37,19 +37,24 @@
#endif
/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
-static int16_t inl_qrdmlah_s16(int16_t src1, int16_t src2,
- int16_t src3, uint32_t *sat)
+static int16_t do_sqrdmlah_h(int16_t src1, int16_t src2, int16_t src3,
+ bool neg, bool round, uint32_t *sat)
{
- /* Simplify:
+ /*
+ * Simplify:
* = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16
* = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15
*/
int32_t ret = (int32_t)src1 * src2;
- ret = ((int32_t)src3 << 15) + ret + (1 << 14);
+ if (neg) {
+ ret = -ret;
+ }
+ ret += ((int32_t)src3 << 15) + (round << 14);
ret >>= 15;
+
if (ret != (int16_t)ret) {
*sat = 1;
- ret = (ret < 0 ? -0x8000 : 0x7fff);
+ ret = (ret < 0 ? INT16_MIN : INT16_MAX);
}
return ret;
}
@@ -58,8 +63,9 @@ uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1,
uint32_t src2, uint32_t src3)
{
uint32_t *sat = &env->vfp.qc[0];
- uint16_t e1 = inl_qrdmlah_s16(src1, src2, src3, sat);
- uint16_t e2 = inl_qrdmlah_s16(src1 >> 16, src2 >> 16, src3 >> 16, sat);
+ uint16_t e1 = do_sqrdmlah_h(src1, src2, src3, false, true, sat);
+ uint16_t e2 = do_sqrdmlah_h(src1 >> 16, src2 >> 16, src3 >> 16,
+ false, true, sat);
return deposit32(e1, 16, 16, e2);
}
@@ -73,35 +79,18 @@ void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm,
uintptr_t i;
for (i = 0; i < opr_sz / 2; ++i) {
- d[i] = inl_qrdmlah_s16(n[i], m[i], d[i], vq);
+ d[i] = do_sqrdmlah_h(n[i], m[i], d[i], false, true, vq);
}
clear_tail(d, opr_sz, simd_maxsz(desc));
}
-/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */
-static int16_t inl_qrdmlsh_s16(int16_t src1, int16_t src2,
- int16_t src3, uint32_t *sat)
-{
- /* Similarly, using subtraction:
- * = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16
- * = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15
- */
- int32_t ret = (int32_t)src1 * src2;
- ret = ((int32_t)src3 << 15) - ret + (1 << 14);
- ret >>= 15;
- if (ret != (int16_t)ret) {
- *sat = 1;
- ret = (ret < 0 ? -0x8000 : 0x7fff);
- }
- return ret;
-}
-
uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1,
uint32_t src2, uint32_t src3)
{
uint32_t *sat = &env->vfp.qc[0];
- uint16_t e1 = inl_qrdmlsh_s16(src1, src2, src3, sat);
- uint16_t e2 = inl_qrdmlsh_s16(src1 >> 16, src2 >> 16, src3 >> 16, sat);
+ uint16_t e1 = do_sqrdmlah_h(src1, src2, src3, true, true, sat);
+ uint16_t e2 = do_sqrdmlah_h(src1 >> 16, src2 >> 16, src3 >> 16,
+ true, true, sat);
return deposit32(e1, 16, 16, e2);
}
@@ -115,19 +104,23 @@ void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm,
uintptr_t i;
for (i = 0; i < opr_sz / 2; ++i) {
- d[i] = inl_qrdmlsh_s16(n[i], m[i], d[i], vq);
+ d[i] = do_sqrdmlah_h(n[i], m[i], d[i], true, true, vq);
}
clear_tail(d, opr_sz, simd_maxsz(desc));
}
/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */
-static int32_t inl_qrdmlah_s32(int32_t src1, int32_t src2,
- int32_t src3, uint32_t *sat)
+static int32_t do_sqrdmlah_s(int32_t src1, int32_t src2, int32_t src3,
+ bool neg, bool round, uint32_t *sat)
{
/* Simplify similarly to int_qrdmlah_s16 above. */
int64_t ret = (int64_t)src1 * src2;
- ret = ((int64_t)src3 << 31) + ret + (1 << 30);
+ if (neg) {
+ ret = -ret;
+ }
+ ret = ((int64_t)src3 << 31) + (round << 30);
ret >>= 31;
+
if (ret != (int32_t)ret) {
*sat = 1;
ret = (ret < 0 ? INT32_MIN : INT32_MAX);
@@ -139,7 +132,7 @@ uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1,
int32_t src2, int32_t src3)
{
uint32_t *sat = &env->vfp.qc[0];
- return inl_qrdmlah_s32(src1, src2, src3, sat);
+ return do_sqrdmlah_s(src1, src2, src3, false, true, sat);
}
void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm,
@@ -152,31 +145,16 @@ void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm,
uintptr_t i;
for (i = 0; i < opr_sz / 4; ++i) {
- d[i] = inl_qrdmlah_s32(n[i], m[i], d[i], vq);
+ d[i] = do_sqrdmlah_s(n[i], m[i], d[i], false, true, vq);
}
clear_tail(d, opr_sz, simd_maxsz(desc));
}
-/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */
-static int32_t inl_qrdmlsh_s32(int32_t src1, int32_t src2,
- int32_t src3, uint32_t *sat)
-{
- /* Simplify similarly to int_qrdmlsh_s16 above. */
- int64_t ret = (int64_t)src1 * src2;
- ret = ((int64_t)src3 << 31) - ret + (1 << 30);
- ret >>= 31;
- if (ret != (int32_t)ret) {
- *sat = 1;
- ret = (ret < 0 ? INT32_MIN : INT32_MAX);
- }
- return ret;
-}
-
uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1,
int32_t src2, int32_t src3)
{
uint32_t *sat = &env->vfp.qc[0];
- return inl_qrdmlsh_s32(src1, src2, src3, sat);
+ return do_sqrdmlah_s(src1, src2, src3, true, true, sat);
}
void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
@@ -189,7 +167,7 @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
uintptr_t i;
for (i = 0; i < opr_sz / 4; ++i) {
- d[i] = inl_qrdmlsh_s32(n[i], m[i], d[i], vq);
+ d[i] = do_sqrdmlah_s(n[i], m[i], d[i], true, true, vq);
}
clear_tail(d, opr_sz, simd_maxsz(desc));
}
--
2.25.1
next prev parent reply other threads:[~2020-08-15 17:41 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-15 1:31 [PATCH 00/20] target/arm: SVE2 preparatory patches Richard Henderson
2020-08-15 1:31 ` [PATCH 01/20] qemu/int128: Add int128_lshift Richard Henderson
2020-08-24 16:40 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 02/20] target/arm: Split out gen_gvec_fn_zz Richard Henderson
2020-08-24 16:40 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 03/20] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn Richard Henderson
2020-08-24 16:40 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 04/20] target/arm: Rearrange {sve,fp}_check_access assert Richard Henderson
2020-08-24 16:59 ` Peter Maydell
2020-08-25 13:47 ` Richard Henderson
2020-08-15 1:31 ` [PATCH 05/20] target/arm: Merge do_vector2_p into do_mov_p Richard Henderson
2020-08-24 16:41 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 06/20] target/arm: Clean up 4-operand predicate expansion Richard Henderson
2020-08-25 11:13 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 07/20] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp Richard Henderson
2020-08-24 16:44 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 08/20] target/arm: Split out gen_gvec_ool_zzzp Richard Henderson
2020-08-24 16:43 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 09/20] target/arm: Merge helper_sve_clr_* and helper_sve_movz_* Richard Henderson
2020-08-25 11:16 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 10/20] target/arm: Split out gen_gvec_ool_zzp Richard Henderson
2020-08-24 16:46 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 11/20] target/arm: Split out gen_gvec_ool_zzz Richard Henderson
2020-08-24 16:47 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 12/20] target/arm: Split out gen_gvec_ool_zz Richard Henderson
2020-08-24 16:47 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 13/20] target/arm: Tidy SVE tszimm shift formats Richard Henderson
2020-08-25 11:18 ` Peter Maydell
2020-08-15 1:31 ` Richard Henderson [this message]
2020-08-25 13:06 ` [PATCH 14/20] target/arm: Generalize inl_qrdmlah_* helper functions Peter Maydell
2020-08-15 1:31 ` [PATCH 15/20] target/arm: Fix sve_uzp_p vs odd vector lengths Richard Henderson
2020-08-25 13:43 ` Peter Maydell
2020-08-25 14:02 ` Richard Henderson
2020-08-25 14:09 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 16/20] target/arm: Fix sve_zip_p " Richard Henderson
2020-08-25 13:49 ` Peter Maydell
2020-08-28 19:26 ` Richard Henderson
2020-08-28 23:01 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 17/20] target/arm: Fix sve_punpk_p " Richard Henderson
2020-08-25 13:53 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 18/20] target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd Richard Henderson
2020-08-25 13:54 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 19/20] target/arm: Convert integer multiply-add " Richard Henderson
2020-08-25 13:55 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 20/20] target/arm: Convert sq{, r}dmulh " Richard Henderson
2020-08-25 13:57 ` Peter Maydell
2020-08-15 17:55 ` [PATCH 00/20] target/arm: SVE2 preparatory patches no-reply
2020-08-27 18:28 ` Peter Maydell
2020-08-27 21:12 ` Richard Henderson
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