From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Laurent Desnogues <laurent.desnogues@gmail.com>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH 15/20] target/arm: Fix sve_uzp_p vs odd vector lengths
Date: Tue, 25 Aug 2020 07:02:47 -0700 [thread overview]
Message-ID: <e31f7e7b-bde8-c434-f692-a098eb4c086f@linaro.org> (raw)
In-Reply-To: <CAFEAcA9KPLqMkzT1ckdQPniJJ9y180YncJxfJ3W4TC_tvq9csg@mail.gmail.com>
On 8/25/20 6:43 AM, Peter Maydell wrote:
> On Sat, 15 Aug 2020 at 02:32, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Missed out on compressing the second half of a predicate
>> with length vl % 512 > 256.
>>
>> Adjust all of the x + (y << s) to x | (y << s) as a
>> general style fix.
>>
>> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/arm/sve_helper.c | 30 +++++++++++++++++++++---------
>> 1 file changed, 21 insertions(+), 9 deletions(-)
>>
>> diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
>> index 4758d46f34..fcb46f150f 100644
>> --- a/target/arm/sve_helper.c
>> +++ b/target/arm/sve_helper.c
>> @@ -1938,7 +1938,7 @@ void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
>> if (oprsz <= 8) {
>> l = compress_bits(n[0] >> odd, esz);
>> h = compress_bits(m[0] >> odd, esz);
>> - d[0] = extract64(l + (h << (4 * oprsz)), 0, 8 * oprsz);
>> + d[0] = l | (h << (4 * oprsz));
>
> Why did we drop the extract64() here ? This doesn't seem
> to correspond to either of the things the commit message
> says we're doing.
Indeed, the commit message could use expansion.
> Also, if oprsz is < 8, don't we need to mask out the high
> bits in l that would otherwise overlap with h << (4 * oprsz) ?
> Are they guaranteed zeroes somehow?
They are guaranteed zeros. See aarch64_sve_narrow_vq.
>> for (i = 0; i < oprsz_16; i++) {
>> l = m[2 * i + 0];
>> h = m[2 * i + 1];
>> l = compress_bits(l >> odd, esz);
>> h = compress_bits(h >> odd, esz);
>> - tmp_m.p[i] = l + (h << 32);
>> + tmp_m.p[i] = l | (h << 32);
>> }
>> - tmp_m.p[i] = compress_bits(m[2 * i] >> odd, esz);
>> + l = m[2 * i + 0];
>> + h = m[2 * i + 1];
>> + l = compress_bits(l >> odd, esz);
>> + h = compress_bits(h >> odd, esz);
>> + tmp_m.p[i] = l | (h << final_shift);
>>
>> swap_memmove(vd + oprsz / 2, &tmp_m, oprsz / 2);
>
> Aren't there cases where the 'n' part of the result doesn't
> end up a whole number of bytes and we have to do a shift as
> well as a byte copy?
No, oprsz will always be a multiple of 2 for predicates.
Just like oprsz will always be a multiple of 16 for sve vectors.
r~
next prev parent reply other threads:[~2020-08-25 14:04 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-15 1:31 [PATCH 00/20] target/arm: SVE2 preparatory patches Richard Henderson
2020-08-15 1:31 ` [PATCH 01/20] qemu/int128: Add int128_lshift Richard Henderson
2020-08-24 16:40 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 02/20] target/arm: Split out gen_gvec_fn_zz Richard Henderson
2020-08-24 16:40 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 03/20] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn Richard Henderson
2020-08-24 16:40 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 04/20] target/arm: Rearrange {sve,fp}_check_access assert Richard Henderson
2020-08-24 16:59 ` Peter Maydell
2020-08-25 13:47 ` Richard Henderson
2020-08-15 1:31 ` [PATCH 05/20] target/arm: Merge do_vector2_p into do_mov_p Richard Henderson
2020-08-24 16:41 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 06/20] target/arm: Clean up 4-operand predicate expansion Richard Henderson
2020-08-25 11:13 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 07/20] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp Richard Henderson
2020-08-24 16:44 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 08/20] target/arm: Split out gen_gvec_ool_zzzp Richard Henderson
2020-08-24 16:43 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 09/20] target/arm: Merge helper_sve_clr_* and helper_sve_movz_* Richard Henderson
2020-08-25 11:16 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 10/20] target/arm: Split out gen_gvec_ool_zzp Richard Henderson
2020-08-24 16:46 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 11/20] target/arm: Split out gen_gvec_ool_zzz Richard Henderson
2020-08-24 16:47 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 12/20] target/arm: Split out gen_gvec_ool_zz Richard Henderson
2020-08-24 16:47 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 13/20] target/arm: Tidy SVE tszimm shift formats Richard Henderson
2020-08-25 11:18 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 14/20] target/arm: Generalize inl_qrdmlah_* helper functions Richard Henderson
2020-08-25 13:06 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 15/20] target/arm: Fix sve_uzp_p vs odd vector lengths Richard Henderson
2020-08-25 13:43 ` Peter Maydell
2020-08-25 14:02 ` Richard Henderson [this message]
2020-08-25 14:09 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 16/20] target/arm: Fix sve_zip_p " Richard Henderson
2020-08-25 13:49 ` Peter Maydell
2020-08-28 19:26 ` Richard Henderson
2020-08-28 23:01 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 17/20] target/arm: Fix sve_punpk_p " Richard Henderson
2020-08-25 13:53 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 18/20] target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd Richard Henderson
2020-08-25 13:54 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 19/20] target/arm: Convert integer multiply-add " Richard Henderson
2020-08-25 13:55 ` Peter Maydell
2020-08-15 1:31 ` [PATCH 20/20] target/arm: Convert sq{, r}dmulh " Richard Henderson
2020-08-25 13:57 ` Peter Maydell
2020-08-15 17:55 ` [PATCH 00/20] target/arm: SVE2 preparatory patches no-reply
2020-08-27 18:28 ` Peter Maydell
2020-08-27 21:12 ` Richard Henderson
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