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From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: Laurent Desnogues <laurent.desnogues@gmail.com>,
	QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH 16/20] target/arm: Fix sve_zip_p vs odd vector lengths
Date: Tue, 25 Aug 2020 14:49:42 +0100	[thread overview]
Message-ID: <CAFEAcA8s==-CGT88P97xFaxcNkOf6WdNYi-3HSwjWRBXh+KQxw@mail.gmail.com> (raw)
In-Reply-To: <20200815013145.539409-17-richard.henderson@linaro.org>

On Sat, 15 Aug 2020 at 02:32, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Wrote too much with low-half zip (zip1) with vl % 512 != 0.
>
> Adjust all of the x + (y << s) to x | (y << s) as a style fix.
>
> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/sve_helper.c | 25 ++++++++++++++-----------
>  1 file changed, 14 insertions(+), 11 deletions(-)
>
> diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
> index fcb46f150f..b8651ae173 100644
> --- a/target/arm/sve_helper.c
> +++ b/target/arm/sve_helper.c
> @@ -1870,6 +1870,7 @@ void HELPER(sve_zip_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
>      intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2;
>      int esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2);
>      intptr_t high = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1);
> +    int esize = 1 << esz;
>      uint64_t *d = vd;
>      intptr_t i;
>
> @@ -1882,33 +1883,35 @@ void HELPER(sve_zip_p)(void *vd, void *vn, void *vm, uint32_t pred_desc)
>          mm = extract64(mm, high * half, half);
>          nn = expand_bits(nn, esz);
>          mm = expand_bits(mm, esz);
> -        d[0] = nn + (mm << (1 << esz));
> +        d[0] = nn | (mm << esize);
>      } else {
> -        ARMPredicateReg tmp_n, tmp_m;
> +        ARMPredicateReg tmp;
>
>          /* We produce output faster than we consume input.
>             Therefore we must be mindful of possible overlap.  */
> -        if ((vn - vd) < (uintptr_t)oprsz) {
> -            vn = memcpy(&tmp_n, vn, oprsz);
> -        }
> -        if ((vm - vd) < (uintptr_t)oprsz) {
> -            vm = memcpy(&tmp_m, vm, oprsz);
> +        if (vd == vn) {
> +            vn = memcpy(&tmp, vn, oprsz);
> +            if (vd == vm) {
> +                vm = vn;
> +            }
> +        } else if (vd == vm) {
> +            vm = memcpy(&tmp, vm, oprsz);

Why is it OK to only check vd==vn etc rather than checking for
overlap the way the old code did ? The commit message doesn't
mention this.

thanks
-- PMM


  reply	other threads:[~2020-08-25 13:51 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-15  1:31 [PATCH 00/20] target/arm: SVE2 preparatory patches Richard Henderson
2020-08-15  1:31 ` [PATCH 01/20] qemu/int128: Add int128_lshift Richard Henderson
2020-08-24 16:40   ` Peter Maydell
2020-08-15  1:31 ` [PATCH 02/20] target/arm: Split out gen_gvec_fn_zz Richard Henderson
2020-08-24 16:40   ` Peter Maydell
2020-08-15  1:31 ` [PATCH 03/20] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn Richard Henderson
2020-08-24 16:40   ` Peter Maydell
2020-08-15  1:31 ` [PATCH 04/20] target/arm: Rearrange {sve,fp}_check_access assert Richard Henderson
2020-08-24 16:59   ` Peter Maydell
2020-08-25 13:47     ` Richard Henderson
2020-08-15  1:31 ` [PATCH 05/20] target/arm: Merge do_vector2_p into do_mov_p Richard Henderson
2020-08-24 16:41   ` Peter Maydell
2020-08-15  1:31 ` [PATCH 06/20] target/arm: Clean up 4-operand predicate expansion Richard Henderson
2020-08-25 11:13   ` Peter Maydell
2020-08-15  1:31 ` [PATCH 07/20] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp Richard Henderson
2020-08-24 16:44   ` Peter Maydell
2020-08-15  1:31 ` [PATCH 08/20] target/arm: Split out gen_gvec_ool_zzzp Richard Henderson
2020-08-24 16:43   ` Peter Maydell
2020-08-15  1:31 ` [PATCH 09/20] target/arm: Merge helper_sve_clr_* and helper_sve_movz_* Richard Henderson
2020-08-25 11:16   ` Peter Maydell
2020-08-15  1:31 ` [PATCH 10/20] target/arm: Split out gen_gvec_ool_zzp Richard Henderson
2020-08-24 16:46   ` Peter Maydell
2020-08-15  1:31 ` [PATCH 11/20] target/arm: Split out gen_gvec_ool_zzz Richard Henderson
2020-08-24 16:47   ` Peter Maydell
2020-08-15  1:31 ` [PATCH 12/20] target/arm: Split out gen_gvec_ool_zz Richard Henderson
2020-08-24 16:47   ` Peter Maydell
2020-08-15  1:31 ` [PATCH 13/20] target/arm: Tidy SVE tszimm shift formats Richard Henderson
2020-08-25 11:18   ` Peter Maydell
2020-08-15  1:31 ` [PATCH 14/20] target/arm: Generalize inl_qrdmlah_* helper functions Richard Henderson
2020-08-25 13:06   ` Peter Maydell
2020-08-15  1:31 ` [PATCH 15/20] target/arm: Fix sve_uzp_p vs odd vector lengths Richard Henderson
2020-08-25 13:43   ` Peter Maydell
2020-08-25 14:02     ` Richard Henderson
2020-08-25 14:09       ` Peter Maydell
2020-08-15  1:31 ` [PATCH 16/20] target/arm: Fix sve_zip_p " Richard Henderson
2020-08-25 13:49   ` Peter Maydell [this message]
2020-08-28 19:26     ` Richard Henderson
2020-08-28 23:01       ` Peter Maydell
2020-08-15  1:31 ` [PATCH 17/20] target/arm: Fix sve_punpk_p " Richard Henderson
2020-08-25 13:53   ` Peter Maydell
2020-08-15  1:31 ` [PATCH 18/20] target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd Richard Henderson
2020-08-25 13:54   ` Peter Maydell
2020-08-15  1:31 ` [PATCH 19/20] target/arm: Convert integer multiply-add " Richard Henderson
2020-08-25 13:55   ` Peter Maydell
2020-08-15  1:31 ` [PATCH 20/20] target/arm: Convert sq{, r}dmulh " Richard Henderson
2020-08-25 13:57   ` Peter Maydell
2020-08-15 17:55 ` [PATCH 00/20] target/arm: SVE2 preparatory patches no-reply
2020-08-27 18:28 ` Peter Maydell
2020-08-27 21:12   ` Richard Henderson

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