From: Yifei Jiang <jiangyifei@huawei.com>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Cc: zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu,
kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com,
Yifei Jiang <jiangyifei@huawei.com>,
Alistair.Francis@wdc.com, yinyipeng1@huawei.com,
palmer@dabbelt.com, wu.wubin@huawei.com, dengkai1@huawei.com
Subject: [PATCH 2/5] target/riscv: Add PMP state description
Date: Tue, 29 Sep 2020 10:03:34 +0800 [thread overview]
Message-ID: <20200929020337.1559-3-jiangyifei@huawei.com> (raw)
In-Reply-To: <20200929020337.1559-1-jiangyifei@huawei.com>
In the case of supporting PMP feature, add PMP state description
to vmstate_riscv_cpu.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/machine.c | 49 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 3451b888b1..b1fc839b43 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -4,6 +4,51 @@
#include "sysemu/kvm.h"
#include "migration/cpu.h"
+static bool pmp_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return riscv_feature(env, RISCV_FEATURE_PMP);
+}
+
+static const VMStateDescription vmstate_pmp_entry = {
+ .name = "cpu/pmp/entry",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(addr_reg, pmp_entry_t),
+ VMSTATE_UINT8(cfg_reg, pmp_entry_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_pmp_addr = {
+ .name = "cpu/pmp/addr",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(sa, pmp_addr_t),
+ VMSTATE_UINTTL(ea, pmp_addr_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_pmp = {
+ .name = "cpu/pmp",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = pmp_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS,
+ 0, vmstate_pmp_entry, pmp_entry_t),
+ VMSTATE_STRUCT_ARRAY(env.pmp_state.addr, RISCVCPU, MAX_RISCV_PMPS,
+ 0, vmstate_pmp_addr, pmp_addr_t),
+ VMSTATE_UINT32(env.pmp_state.num_rules, RISCVCPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 1,
@@ -55,5 +100,9 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.mstatush, RISCVCPU),
#endif
VMSTATE_END_OF_LIST()
+ },
+ .subsections = (const VMStateDescription * []) {
+ &vmstate_pmp,
+ NULL
}
};
--
2.19.1
next prev parent reply other threads:[~2020-09-29 2:05 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-29 2:03 [PATCH 0/5] Support RISC-V migration Yifei Jiang
2020-09-29 2:03 ` [PATCH 1/5] target/riscv: Add basic vmstate description of CPU Yifei Jiang
2020-10-01 17:23 ` Richard Henderson
2020-10-09 8:11 ` Jiangyifei
2020-09-29 2:03 ` Yifei Jiang [this message]
2020-10-05 22:10 ` [PATCH 2/5] target/riscv: Add PMP state description Alistair Francis
2020-10-09 8:33 ` Jiangyifei
2020-09-29 2:03 ` [PATCH 3/5] target/riscv: Add H extention " Yifei Jiang
2020-10-01 17:28 ` Richard Henderson
2020-10-05 22:09 ` Alistair Francis
2020-10-09 8:29 ` Jiangyifei
2020-09-29 2:03 ` [PATCH 4/5] target/riscv: Add V " Yifei Jiang
2020-10-01 17:30 ` Richard Henderson
2020-09-29 2:03 ` [PATCH 5/5] target/riscv: Add sifive_plic vmstate Yifei Jiang
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