From: Richard Henderson <richard.henderson@linaro.org>
To: Yifei Jiang <jiangyifei@huawei.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu,
kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com,
Alistair.Francis@wdc.com, yinyipeng1@huawei.com,
palmer@dabbelt.com, wu.wubin@huawei.com, dengkai1@huawei.com
Subject: Re: [PATCH 4/5] target/riscv: Add V extention state description
Date: Thu, 1 Oct 2020 12:30:21 -0500 [thread overview]
Message-ID: <adfc3dc2-606f-5670-4b3b-c0719826a60e@linaro.org> (raw)
In-Reply-To: <20200929020337.1559-5-jiangyifei@huawei.com>
On 9/28/20 9:03 PM, Yifei Jiang wrote:
> In the case of supporting V extention, add V extention description
> to vmstate_riscv_cpu.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> ---
> target/riscv/machine.c | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Though of course this is racing with the v1.0 patch set, which changes the set
of vector csrs.
r~
next prev parent reply other threads:[~2020-10-01 18:01 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-29 2:03 [PATCH 0/5] Support RISC-V migration Yifei Jiang
2020-09-29 2:03 ` [PATCH 1/5] target/riscv: Add basic vmstate description of CPU Yifei Jiang
2020-10-01 17:23 ` Richard Henderson
2020-10-09 8:11 ` Jiangyifei
2020-09-29 2:03 ` [PATCH 2/5] target/riscv: Add PMP state description Yifei Jiang
2020-10-05 22:10 ` Alistair Francis
2020-10-09 8:33 ` Jiangyifei
2020-09-29 2:03 ` [PATCH 3/5] target/riscv: Add H extention " Yifei Jiang
2020-10-01 17:28 ` Richard Henderson
2020-10-05 22:09 ` Alistair Francis
2020-10-09 8:29 ` Jiangyifei
2020-09-29 2:03 ` [PATCH 4/5] target/riscv: Add V " Yifei Jiang
2020-10-01 17:30 ` Richard Henderson [this message]
2020-09-29 2:03 ` [PATCH 5/5] target/riscv: Add sifive_plic vmstate Yifei Jiang
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