From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Zhanghailiang <zhang.zhanghailiang@huawei.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
"Zhangxiaofeng \(F\)" <victor.zhangxiaofeng@huawei.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Yifei Jiang <jiangyifei@huawei.com>,
yinyipeng <yinyipeng1@huawei.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
"Wubin \(H\)" <wu.wubin@huawei.com>,
"dengkai \(A\)" <dengkai1@huawei.com>
Subject: Re: [PATCH 3/5] target/riscv: Add H extention state description
Date: Mon, 5 Oct 2020 15:09:34 -0700 [thread overview]
Message-ID: <CAKmqyKMzZ3W130jG973PWBQ52zBLVfSP+=Xbp7Cdk4NpuHDkgw@mail.gmail.com> (raw)
In-Reply-To: <2e725e26-3952-dbd2-c4aa-d9e933406220@linaro.org>
On Thu, Oct 1, 2020 at 10:56 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 9/28/20 9:03 PM, Yifei Jiang wrote:
> > + VMSTATE_UINTTL(env.vsstatus, RISCVCPU),
> > + VMSTATE_UINTTL(env.vstvec, RISCVCPU),
> > + VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
> > + VMSTATE_UINTTL(env.vsepc, RISCVCPU),
> > + VMSTATE_UINTTL(env.vscause, RISCVCPU),
> > + VMSTATE_UINTTL(env.vstval, RISCVCPU),
> > + VMSTATE_UINTTL(env.vsatp, RISCVCPU),
>
> So... if I understand things correctly, this is synthetic state, internal to
> QEMU. It is generally better to only serialize architectural state, so that if
> qemu internals are rearranged, it is easy to decide on the correct sequence of
> operations.
I don't think the virtual registers are synthetic, they contain what
the guest Hypervisor/Hypervisor guest wrote to those CSRs. I don't
think we could re-generate them from anything else.
There are some other registers in this series that I think can be
re-generated. The PMP is a good example of that, where the PMP config
data could be re-generated from the CSRs.
Alistair
>
> It seems like this should be re-generated with a post_load hook, calling some
> of the code currently in riscv_cpu_swap_hypervisor_regs(). Note that some
> minor rearrangement would be needed to call that code from this new context.
>
>
> r~
>
next prev parent reply other threads:[~2020-10-05 22:22 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-29 2:03 [PATCH 0/5] Support RISC-V migration Yifei Jiang
2020-09-29 2:03 ` [PATCH 1/5] target/riscv: Add basic vmstate description of CPU Yifei Jiang
2020-10-01 17:23 ` Richard Henderson
2020-10-09 8:11 ` Jiangyifei
2020-09-29 2:03 ` [PATCH 2/5] target/riscv: Add PMP state description Yifei Jiang
2020-10-05 22:10 ` Alistair Francis
2020-10-09 8:33 ` Jiangyifei
2020-09-29 2:03 ` [PATCH 3/5] target/riscv: Add H extention " Yifei Jiang
2020-10-01 17:28 ` Richard Henderson
2020-10-05 22:09 ` Alistair Francis [this message]
2020-10-09 8:29 ` Jiangyifei
2020-09-29 2:03 ` [PATCH 4/5] target/riscv: Add V " Yifei Jiang
2020-10-01 17:30 ` Richard Henderson
2020-09-29 2:03 ` [PATCH 5/5] target/riscv: Add sifive_plic vmstate Yifei Jiang
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