From: Jiangyifei <jiangyifei@huawei.com>
To: Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: Zhanghailiang <zhang.zhanghailiang@huawei.com>,
"sagark@eecs.berkeley.edu" <sagark@eecs.berkeley.edu>,
"kbastian@mail.uni-paderborn.de" <kbastian@mail.uni-paderborn.de>,
"Zhangxiaofeng \(F\)" <victor.zhangxiaofeng@huawei.com>,
"Alistair.Francis@wdc.com" <Alistair.Francis@wdc.com>,
yinyipeng <yinyipeng1@huawei.com>,
"palmer@dabbelt.com" <palmer@dabbelt.com>,
"Wubin \(H\)" <wu.wubin@huawei.com>,
"dengkai \(A\)" <dengkai1@huawei.com>
Subject: RE: [PATCH 1/5] target/riscv: Add basic vmstate description of CPU
Date: Fri, 9 Oct 2020 08:11:16 +0000 [thread overview]
Message-ID: <8882324c7f3d46e08d9c2fb902c14cac@huawei.com> (raw)
In-Reply-To: <b70824e1-aed9-1d72-21e8-ac444ccc9a09@linaro.org>
> -----Original Message-----
> From: Richard Henderson [mailto:richard.henderson@linaro.org]
> Sent: Friday, October 2, 2020 1:23 AM
> To: Jiangyifei <jiangyifei@huawei.com>; qemu-devel@nongnu.org;
> qemu-riscv@nongnu.org
> Cc: Zhanghailiang <zhang.zhanghailiang@huawei.com>;
> sagark@eecs.berkeley.edu; kbastian@mail.uni-paderborn.de; Zhangxiaofeng
> (F) <victor.zhangxiaofeng@huawei.com>; Alistair.Francis@wdc.com; yinyipeng
> <yinyipeng1@huawei.com>; palmer@dabbelt.com; Wubin (H)
> <wu.wubin@huawei.com>; dengkai (A) <dengkai1@huawei.com>
> Subject: Re: [PATCH 1/5] target/riscv: Add basic vmstate description of CPU
>
> On 9/28/20 9:03 PM, Yifei Jiang wrote:
> > --- /dev/null
> > +++ b/target/riscv/machine.c
> > @@ -0,0 +1,59 @@
> > +#include "qemu/osdep.h"
> > +#include "cpu.h"
>
> All new files must contain license boilerplate.
>
> Otherwise, considering the followups, this seems ok.
>
Thanks, I'll add license boilerplate in the next series.
Yifei
>
> r~
next prev parent reply other threads:[~2020-10-09 8:12 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-29 2:03 [PATCH 0/5] Support RISC-V migration Yifei Jiang
2020-09-29 2:03 ` [PATCH 1/5] target/riscv: Add basic vmstate description of CPU Yifei Jiang
2020-10-01 17:23 ` Richard Henderson
2020-10-09 8:11 ` Jiangyifei [this message]
2020-09-29 2:03 ` [PATCH 2/5] target/riscv: Add PMP state description Yifei Jiang
2020-10-05 22:10 ` Alistair Francis
2020-10-09 8:33 ` Jiangyifei
2020-09-29 2:03 ` [PATCH 3/5] target/riscv: Add H extention " Yifei Jiang
2020-10-01 17:28 ` Richard Henderson
2020-10-05 22:09 ` Alistair Francis
2020-10-09 8:29 ` Jiangyifei
2020-09-29 2:03 ` [PATCH 4/5] target/riscv: Add V " Yifei Jiang
2020-10-01 17:30 ` Richard Henderson
2020-09-29 2:03 ` [PATCH 5/5] target/riscv: Add sifive_plic vmstate Yifei Jiang
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