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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Bin Meng <bin.meng@windriver.com>,
	qemu-devel@nongnu.org, Bin Meng <bmeng.cn@gmail.com>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Jean-Christophe Dubois" <jcd@tribudubois.net>,
	qemu-arm@nongnu.org, "Peter Chubb" <peter.chubb@nicta.com.au>
Subject: [RFC PATCH v6 09/11] hw/ssi: imx_spi: Round up the burst length to be multiple of 8
Date: Tue, 12 Jan 2021 19:35:27 +0100	[thread overview]
Message-ID: <20210112183529.2011863-10-f4bug@amsat.org> (raw)
In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org>

From: Bin Meng <bin.meng@windriver.com>

Current implementation of the imx spi controller expects the burst
length to be multiple of 8, which is the most common use case.

In case the burst length is not what we expect, log it to give user
a chance to notice it, and round it up to be multiple of 8.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20210112145526.31095-5-bmeng.cn@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/ssi/imx_spi.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index 2f9e800dd3a..638959daa08 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -129,7 +129,20 @@ static uint8_t imx_spi_selected_channel(IMXSPIState *s)
 
 static uint32_t imx_spi_burst_length(IMXSPIState *s)
 {
-    return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
+    uint32_t burst;
+
+    burst = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
+    if (burst % 8) {
+        qemu_log_mask(LOG_UNIMP,
+                      "[%s]%s: burst length (%d) not multiple of 8!\n",
+                      TYPE_IMX_SPI, __func__, burst);
+        burst = ROUND_UP(burst, 8);
+        qemu_log_mask(LOG_UNIMP,
+                      "[%s]%s: burst length rounded up to %d; this may not work.\n",
+                      TYPE_IMX_SPI, __func__, burst);
+    }
+
+    return burst;
 }
 
 static bool imx_spi_is_enabled(IMXSPIState *s)
-- 
2.26.2



  parent reply	other threads:[~2021-01-12 19:03 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-12 18:35 [RFC PATCH v6 00/11] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Philippe Mathieu-Daudé
2021-01-12 18:35 ` [RFC PATCH v6 01/11] hw/ssi: imx_spi: Use a macro for number of chip selects supported Philippe Mathieu-Daudé
2021-01-13 13:35   ` Juan Quintela
2021-01-12 18:35 ` [RFC PATCH v6 02/11] hw/ssi: imx_spi: Remove pointless variable initialization Philippe Mathieu-Daudé
2021-01-13 13:35   ` Juan Quintela
2021-01-12 18:35 ` [RFC PATCH v6 03/11] hw/ssi: imx_spi: Convert some debug printf()s to trace events Philippe Mathieu-Daudé
2021-01-13 13:36   ` Juan Quintela
2021-01-12 18:35 ` [RFC PATCH v6 04/11] hw/ssi: imx_spi: Reduce 'change_mask' variable scope Philippe Mathieu-Daudé
2021-01-13 13:41   ` Juan Quintela
2021-01-13 13:47     ` Juan Quintela
2021-01-15 15:24       ` Philippe Mathieu-Daudé
2021-01-12 18:35 ` [RFC PATCH v6 05/11] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Philippe Mathieu-Daudé
2021-01-13 13:43   ` Juan Quintela
2021-01-12 18:35 ` [RFC PATCH v6 06/11] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Philippe Mathieu-Daudé
2021-01-13 13:46   ` Juan Quintela
2021-01-12 18:35 ` [RFC PATCH v6 07/11] hw/ssi: imx_spi: Rework imx_spi_write() " Philippe Mathieu-Daudé
2021-01-12 18:35 ` [RFC PATCH v6 08/11] hw/ssi: imx_spi: Disable chip selects when controller is disabled Philippe Mathieu-Daudé
2021-01-12 18:35 ` Philippe Mathieu-Daudé [this message]
2021-01-12 18:35 ` [RFC PATCH v6 10/11] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Philippe Mathieu-Daudé
2021-01-12 18:35 ` [RFC PATCH v6 11/11] hw/ssi: imx_spi: Correct tx and rx fifo endianness Philippe Mathieu-Daudé
2021-01-13  3:29 ` [RFC PATCH v6 00/11] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Bin Meng
2021-01-13  7:53   ` Philippe Mathieu-Daudé
2021-01-13 13:27     ` Bin Meng
2021-01-13 14:16       ` Bin Meng
2021-01-13 17:56       ` Philippe Mathieu-Daudé
2021-01-14 16:00         ` Philippe Mathieu-Daudé

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