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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Bin Meng <bin.meng@windriver.com>,
	qemu-devel@nongnu.org, Bin Meng <bmeng.cn@gmail.com>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Jean-Christophe Dubois" <jcd@tribudubois.net>,
	qemu-arm@nongnu.org, "Peter Chubb" <peter.chubb@nicta.com.au>
Subject: [RFC PATCH v6 06/11] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled
Date: Tue, 12 Jan 2021 19:35:24 +0100	[thread overview]
Message-ID: <20210112183529.2011863-7-f4bug@amsat.org> (raw)
In-Reply-To: <20210112183529.2011863-1-f4bug@amsat.org>

When the block is disabled, it stay it is 'internal reset logic'
(internal clocks are gated off). Reading any register returns
its reset value. Only update this value if the device is enabled.

Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
     chapter 21.7.3: Control Register (ECSPIx_CONREG)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/ssi/imx_spi.c | 60 +++++++++++++++++++++++-------------------------
 1 file changed, 29 insertions(+), 31 deletions(-)

diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index 96aecc8fa28..7ac9da0f1d2 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -270,42 +270,40 @@ static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
         return 0;
     }
 
-    switch (index) {
-    case ECSPI_RXDATA:
-        if (!imx_spi_is_enabled(s)) {
-            value = 0;
-        } else if (fifo32_is_empty(&s->rx_fifo)) {
-            /* value is undefined */
-            value = 0xdeadbeef;
-        } else {
-            /* read from the RX FIFO */
-            value = fifo32_pop(&s->rx_fifo);
+    value = s->regs[index];
+
+    if (imx_spi_is_enabled(s)) {
+        switch (index) {
+        case ECSPI_RXDATA:
+            if (fifo32_is_empty(&s->rx_fifo)) {
+                /* value is undefined */
+                value = 0xdeadbeef;
+            } else {
+                /* read from the RX FIFO */
+                value = fifo32_pop(&s->rx_fifo);
+            }
+            break;
+        case ECSPI_TXDATA:
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "[%s]%s: Trying to read from TX FIFO\n",
+                          TYPE_IMX_SPI, __func__);
+
+            /* Reading from TXDATA gives 0 */
+            break;
+        case ECSPI_MSGDATA:
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "[%s]%s: Trying to read from MSG FIFO\n",
+                          TYPE_IMX_SPI, __func__);
+            /* Reading from MSGDATA gives 0 */
+            break;
+        default:
+            break;
         }
 
-        break;
-    case ECSPI_TXDATA:
-        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n",
-                      TYPE_IMX_SPI, __func__);
-
-        /* Reading from TXDATA gives 0 */
-
-        break;
-    case ECSPI_MSGDATA:
-        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n",
-                      TYPE_IMX_SPI, __func__);
-
-        /* Reading from MSGDATA gives 0 */
-
-        break;
-    default:
-        value = s->regs[index];
-        break;
+        imx_spi_update_irq(s);
     }
-
     trace_imx_spi_read(index, imx_spi_reg_name(index), value);
 
-    imx_spi_update_irq(s);
-
     return (uint64_t)value;
 }
 
-- 
2.26.2



  parent reply	other threads:[~2021-01-12 18:59 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-12 18:35 [RFC PATCH v6 00/11] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Philippe Mathieu-Daudé
2021-01-12 18:35 ` [RFC PATCH v6 01/11] hw/ssi: imx_spi: Use a macro for number of chip selects supported Philippe Mathieu-Daudé
2021-01-13 13:35   ` Juan Quintela
2021-01-12 18:35 ` [RFC PATCH v6 02/11] hw/ssi: imx_spi: Remove pointless variable initialization Philippe Mathieu-Daudé
2021-01-13 13:35   ` Juan Quintela
2021-01-12 18:35 ` [RFC PATCH v6 03/11] hw/ssi: imx_spi: Convert some debug printf()s to trace events Philippe Mathieu-Daudé
2021-01-13 13:36   ` Juan Quintela
2021-01-12 18:35 ` [RFC PATCH v6 04/11] hw/ssi: imx_spi: Reduce 'change_mask' variable scope Philippe Mathieu-Daudé
2021-01-13 13:41   ` Juan Quintela
2021-01-13 13:47     ` Juan Quintela
2021-01-15 15:24       ` Philippe Mathieu-Daudé
2021-01-12 18:35 ` [RFC PATCH v6 05/11] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Philippe Mathieu-Daudé
2021-01-13 13:43   ` Juan Quintela
2021-01-12 18:35 ` Philippe Mathieu-Daudé [this message]
2021-01-13 13:46   ` [RFC PATCH v6 06/11] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Juan Quintela
2021-01-12 18:35 ` [RFC PATCH v6 07/11] hw/ssi: imx_spi: Rework imx_spi_write() " Philippe Mathieu-Daudé
2021-01-12 18:35 ` [RFC PATCH v6 08/11] hw/ssi: imx_spi: Disable chip selects when controller is disabled Philippe Mathieu-Daudé
2021-01-12 18:35 ` [RFC PATCH v6 09/11] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Philippe Mathieu-Daudé
2021-01-12 18:35 ` [RFC PATCH v6 10/11] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Philippe Mathieu-Daudé
2021-01-12 18:35 ` [RFC PATCH v6 11/11] hw/ssi: imx_spi: Correct tx and rx fifo endianness Philippe Mathieu-Daudé
2021-01-13  3:29 ` [RFC PATCH v6 00/11] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Bin Meng
2021-01-13  7:53   ` Philippe Mathieu-Daudé
2021-01-13 13:27     ` Bin Meng
2021-01-13 14:16       ` Bin Meng
2021-01-13 17:56       ` Philippe Mathieu-Daudé
2021-01-14 16:00         ` Philippe Mathieu-Daudé

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