From: Juan Quintela <quintela@redhat.com>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Alistair Francis <alistair@alistair23.me>,
Bin Meng <bin.meng@windriver.com>,
qemu-devel@nongnu.org,
Jean-Christophe Dubois <jcd@tribudubois.net>,
qemu-arm@nongnu.org, Peter Chubb <peter.chubb@nicta.com.au>,
Bin Meng <bmeng.cn@gmail.com>
Subject: Re: [RFC PATCH v6 04/11] hw/ssi: imx_spi: Reduce 'change_mask' variable scope
Date: Wed, 13 Jan 2021 14:47:47 +0100 [thread overview]
Message-ID: <875z41gd8c.fsf@secure.mitica> (raw)
In-Reply-To: <87im81gdig.fsf@secure.mitica> (Juan Quintela's message of "Wed, 13 Jan 2021 14:41:43 +0100")
Juan Quintela <quintela@redhat.com> wrote:
> Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> I think this one is wrong.
Wrong is a strong word. I mean that it changes behaviour and the commit
message don't talk about changing behaviour.
Later, Juan.
>
>
>> ---
>> hw/ssi/imx_spi.c | 3 +--
>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
>> index 35ab33c0511..bcc535f2893 100644
>> --- a/hw/ssi/imx_spi.c
>> +++ b/hw/ssi/imx_spi.c
>> @@ -303,7 +303,6 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
>> {
>> IMXSPIState *s = opaque;
>> uint32_t index = offset >> 2;
>> - uint32_t change_mask;
>>
>> if (index >= ECSPI_MAX) {
>> qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
>> @@ -313,7 +312,6 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
>>
>> trace_imx_spi_write(index, imx_spi_reg_name(index), value);
>>
>> - change_mask = s->regs[index] ^ value;
>>
>> switch (index) {
>> case ECSPI_RXDATA:
>> @@ -357,6 +355,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
>> }
>>
>> if (imx_spi_channel_is_master(s)) {
>> + uint32_t change_mask = s->regs[index] ^ value;
>> int i;
>>
>> /* We are in master mode */
>
> The code does:
>
> change_mask = s->regs[index] ^ value;
>
> switch (index) {
>
> ...
>
> case ECSPI_CONREG:
> s->regs[ECSPI_CONREG] = value; <<---- here
>
> if (!imx_spi_is_enabled(s)) {
> /* device is disabled, so this is a reset */
> imx_spi_reset(DEVICE(s));
> return;
> }
>
> if (imx_spi_channel_is_master(s)) {
> int i;
> >>>>> You are setting change_mask here.
>
> At this point, s->regs[index] has a new value in "here".
>
> Later, Juan.
next prev parent reply other threads:[~2021-01-13 13:50 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-12 18:35 [RFC PATCH v6 00/11] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Philippe Mathieu-Daudé
2021-01-12 18:35 ` [RFC PATCH v6 01/11] hw/ssi: imx_spi: Use a macro for number of chip selects supported Philippe Mathieu-Daudé
2021-01-13 13:35 ` Juan Quintela
2021-01-12 18:35 ` [RFC PATCH v6 02/11] hw/ssi: imx_spi: Remove pointless variable initialization Philippe Mathieu-Daudé
2021-01-13 13:35 ` Juan Quintela
2021-01-12 18:35 ` [RFC PATCH v6 03/11] hw/ssi: imx_spi: Convert some debug printf()s to trace events Philippe Mathieu-Daudé
2021-01-13 13:36 ` Juan Quintela
2021-01-12 18:35 ` [RFC PATCH v6 04/11] hw/ssi: imx_spi: Reduce 'change_mask' variable scope Philippe Mathieu-Daudé
2021-01-13 13:41 ` Juan Quintela
2021-01-13 13:47 ` Juan Quintela [this message]
2021-01-15 15:24 ` Philippe Mathieu-Daudé
2021-01-12 18:35 ` [RFC PATCH v6 05/11] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Philippe Mathieu-Daudé
2021-01-13 13:43 ` Juan Quintela
2021-01-12 18:35 ` [RFC PATCH v6 06/11] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Philippe Mathieu-Daudé
2021-01-13 13:46 ` Juan Quintela
2021-01-12 18:35 ` [RFC PATCH v6 07/11] hw/ssi: imx_spi: Rework imx_spi_write() " Philippe Mathieu-Daudé
2021-01-12 18:35 ` [RFC PATCH v6 08/11] hw/ssi: imx_spi: Disable chip selects when controller is disabled Philippe Mathieu-Daudé
2021-01-12 18:35 ` [RFC PATCH v6 09/11] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Philippe Mathieu-Daudé
2021-01-12 18:35 ` [RFC PATCH v6 10/11] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Philippe Mathieu-Daudé
2021-01-12 18:35 ` [RFC PATCH v6 11/11] hw/ssi: imx_spi: Correct tx and rx fifo endianness Philippe Mathieu-Daudé
2021-01-13 3:29 ` [RFC PATCH v6 00/11] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Bin Meng
2021-01-13 7:53 ` Philippe Mathieu-Daudé
2021-01-13 13:27 ` Bin Meng
2021-01-13 14:16 ` Bin Meng
2021-01-13 17:56 ` Philippe Mathieu-Daudé
2021-01-14 16:00 ` Philippe Mathieu-Daudé
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