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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 09/21] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled
Date: Tue,  2 Feb 2021 17:55:05 +0000	[thread overview]
Message-ID: <20210202175517.28729-10-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210202175517.28729-1-peter.maydell@linaro.org>

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

When the block is disabled, it stay it is 'internal reset logic'
(internal clocks are gated off). Reading any register returns
its reset value. Only update this value if the device is enabled.

Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
     chapter 21.7.3: Control Register (ECSPIx_CONREG)

Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Message-id: 20210129132323.30946-6-bmeng.cn@gmail.com
Message-Id: <20210115153049.3353008-5-f4bug@amsat.org>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/ssi/imx_spi.c | 60 +++++++++++++++++++++++-------------------------
 1 file changed, 29 insertions(+), 31 deletions(-)

diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index e85be6ae607..21e2c9dea3e 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -279,42 +279,40 @@ static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
         return 0;
     }
 
-    switch (index) {
-    case ECSPI_RXDATA:
-        if (!imx_spi_is_enabled(s)) {
-            value = 0;
-        } else if (fifo32_is_empty(&s->rx_fifo)) {
-            /* value is undefined */
-            value = 0xdeadbeef;
-        } else {
-            /* read from the RX FIFO */
-            value = fifo32_pop(&s->rx_fifo);
+    value = s->regs[index];
+
+    if (imx_spi_is_enabled(s)) {
+        switch (index) {
+        case ECSPI_RXDATA:
+            if (fifo32_is_empty(&s->rx_fifo)) {
+                /* value is undefined */
+                value = 0xdeadbeef;
+            } else {
+                /* read from the RX FIFO */
+                value = fifo32_pop(&s->rx_fifo);
+            }
+            break;
+        case ECSPI_TXDATA:
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "[%s]%s: Trying to read from TX FIFO\n",
+                          TYPE_IMX_SPI, __func__);
+
+            /* Reading from TXDATA gives 0 */
+            break;
+        case ECSPI_MSGDATA:
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "[%s]%s: Trying to read from MSG FIFO\n",
+                          TYPE_IMX_SPI, __func__);
+            /* Reading from MSGDATA gives 0 */
+            break;
+        default:
+            break;
         }
 
-        break;
-    case ECSPI_TXDATA:
-        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n",
-                      TYPE_IMX_SPI, __func__);
-
-        /* Reading from TXDATA gives 0 */
-
-        break;
-    case ECSPI_MSGDATA:
-        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n",
-                      TYPE_IMX_SPI, __func__);
-
-        /* Reading from MSGDATA gives 0 */
-
-        break;
-    default:
-        value = s->regs[index];
-        break;
+        imx_spi_update_irq(s);
     }
-
     DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value);
 
-    imx_spi_update_irq(s);
-
     return (uint64_t)value;
 }
 
-- 
2.20.1



  parent reply	other threads:[~2021-02-02 18:11 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-02 17:54 [PULL 00/21] target-arm queue Peter Maydell
2021-02-02 17:54 ` [PULL 01/21] hw/intc/arm_gic: Allow to use QTest without crashing Peter Maydell
2021-02-02 17:54 ` [PULL 02/21] hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled Peter Maydell
2021-02-02 17:54 ` [PULL 03/21] hw/char/exynos4210_uart: Fix missing call to report ready for input Peter Maydell
2021-02-02 17:55 ` [PULL 04/21] hw/arm/smmuv3: Fix addr_mask for range-based invalidation Peter Maydell
2021-02-02 17:55 ` [PULL 05/21] hw/ssi: imx_spi: Use a macro for number of chip selects supported Peter Maydell
2021-02-02 17:55 ` [PULL 06/21] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() Peter Maydell
2021-02-02 17:55 ` [PULL 07/21] hw/ssi: imx_spi: Remove pointless variable initialization Peter Maydell
2021-02-02 17:55 ` [PULL 08/21] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Peter Maydell
2021-02-02 17:55 ` Peter Maydell [this message]
2021-02-02 17:55 ` [PULL 10/21] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled Peter Maydell
2021-02-02 17:55 ` [PULL 11/21] hw/ssi: imx_spi: Disable chip selects when controller is disabled Peter Maydell
2021-02-02 17:55 ` [PULL 12/21] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Peter Maydell
2021-02-02 17:55 ` [PULL 13/21] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Peter Maydell
2021-02-02 17:55 ` [PULL 14/21] hw/ssi: imx_spi: Correct tx and rx fifo endianness Peter Maydell
2021-02-02 17:55 ` [PULL 15/21] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register Peter Maydell
2021-02-02 17:55 ` [PULL 16/21] hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ Peter Maydell
2021-02-02 17:55 ` [PULL 17/21] hw/arm/exynos4210: " Peter Maydell
2021-02-02 17:55 ` [PULL 18/21] hw/arm/xlnx-versal: Versal SoC requires ZDMA Peter Maydell
2021-02-02 17:55 ` [PULL 19/21] hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals Peter Maydell
2021-02-02 17:55 ` [PULL 20/21] hw/net/can: ZynqMP CAN device requires PTIMER Peter Maydell
2021-02-02 17:55 ` [PULL 21/21] hw/arm: Display CPU type in machine description Peter Maydell
2021-02-03  9:22 ` [PULL 00/21] target-arm queue Philippe Mathieu-Daudé
2021-02-03 10:12   ` P J P

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