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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 08/21] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value
Date: Tue,  2 Feb 2021 17:55:04 +0000	[thread overview]
Message-ID: <20210202175517.28729-9-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210202175517.28729-1-peter.maydell@linaro.org>

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

When the block is disabled, all registers are reset with the
exception of the ECSPI_CONREG. It is initialized to zero
when the instance is created.

Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
     chapter 21.7.3: Control Register (ECSPIx_CONREG)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210129132323.30946-5-bmeng.cn@gmail.com
[bmeng: add a 'common_reset' function that does most of reset operation]
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/ssi/imx_spi.c | 32 ++++++++++++++++++++++++--------
 1 file changed, 24 insertions(+), 8 deletions(-)

diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index 8fb3c9b6d1b..e85be6ae607 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -228,15 +228,23 @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
             fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
 }
 
-static void imx_spi_reset(DeviceState *dev)
+static void imx_spi_common_reset(IMXSPIState *s)
 {
-    IMXSPIState *s = IMX_SPI(dev);
+    int i;
 
-    DPRINTF("\n");
-
-    memset(s->regs, 0, sizeof(s->regs));
-
-    s->regs[ECSPI_STATREG] = 0x00000003;
+    for (i = 0; i < ARRAY_SIZE(s->regs); i++) {
+        switch (i) {
+        case ECSPI_CONREG:
+            /* CONREG is not updated on soft reset */
+            break;
+        case ECSPI_STATREG:
+            s->regs[i] = 0x00000003;
+            break;
+        default:
+            s->regs[i] = 0;
+            break;
+        }
+    }
 
     imx_spi_rxfifo_reset(s);
     imx_spi_txfifo_reset(s);
@@ -246,11 +254,19 @@ static void imx_spi_reset(DeviceState *dev)
 
 static void imx_spi_soft_reset(IMXSPIState *s)
 {
-    imx_spi_reset(DEVICE(s));
+    imx_spi_common_reset(s);
 
     imx_spi_update_irq(s);
 }
 
+static void imx_spi_reset(DeviceState *dev)
+{
+    IMXSPIState *s = IMX_SPI(dev);
+
+    imx_spi_common_reset(s);
+    s->regs[ECSPI_CONREG] = 0;
+}
+
 static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
 {
     uint32_t value = 0;
-- 
2.20.1



  parent reply	other threads:[~2021-02-02 18:08 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-02 17:54 [PULL 00/21] target-arm queue Peter Maydell
2021-02-02 17:54 ` [PULL 01/21] hw/intc/arm_gic: Allow to use QTest without crashing Peter Maydell
2021-02-02 17:54 ` [PULL 02/21] hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled Peter Maydell
2021-02-02 17:54 ` [PULL 03/21] hw/char/exynos4210_uart: Fix missing call to report ready for input Peter Maydell
2021-02-02 17:55 ` [PULL 04/21] hw/arm/smmuv3: Fix addr_mask for range-based invalidation Peter Maydell
2021-02-02 17:55 ` [PULL 05/21] hw/ssi: imx_spi: Use a macro for number of chip selects supported Peter Maydell
2021-02-02 17:55 ` [PULL 06/21] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() Peter Maydell
2021-02-02 17:55 ` [PULL 07/21] hw/ssi: imx_spi: Remove pointless variable initialization Peter Maydell
2021-02-02 17:55 ` Peter Maydell [this message]
2021-02-02 17:55 ` [PULL 09/21] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Peter Maydell
2021-02-02 17:55 ` [PULL 10/21] hw/ssi: imx_spi: Rework imx_spi_write() " Peter Maydell
2021-02-02 17:55 ` [PULL 11/21] hw/ssi: imx_spi: Disable chip selects when controller is disabled Peter Maydell
2021-02-02 17:55 ` [PULL 12/21] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Peter Maydell
2021-02-02 17:55 ` [PULL 13/21] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Peter Maydell
2021-02-02 17:55 ` [PULL 14/21] hw/ssi: imx_spi: Correct tx and rx fifo endianness Peter Maydell
2021-02-02 17:55 ` [PULL 15/21] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register Peter Maydell
2021-02-02 17:55 ` [PULL 16/21] hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ Peter Maydell
2021-02-02 17:55 ` [PULL 17/21] hw/arm/exynos4210: " Peter Maydell
2021-02-02 17:55 ` [PULL 18/21] hw/arm/xlnx-versal: Versal SoC requires ZDMA Peter Maydell
2021-02-02 17:55 ` [PULL 19/21] hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals Peter Maydell
2021-02-02 17:55 ` [PULL 20/21] hw/net/can: ZynqMP CAN device requires PTIMER Peter Maydell
2021-02-02 17:55 ` [PULL 21/21] hw/arm: Display CPU type in machine description Peter Maydell
2021-02-03  9:22 ` [PULL 00/21] target-arm queue Philippe Mathieu-Daudé
2021-02-03 10:12   ` P J P

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