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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 10/21] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled
Date: Tue,  2 Feb 2021 17:55:06 +0000	[thread overview]
Message-ID: <20210202175517.28729-11-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210202175517.28729-1-peter.maydell@linaro.org>

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

When the block is disabled, only the ECSPI_CONREG register can
be modified. Setting the EN bit enabled the device, clearing it
"disables the block and resets the internal logic with the
exception of the ECSPI_CONREG" register.

Ignore all other registers write except ECSPI_CONREG when the
block is disabled.

Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
     chapter 21.7.3: Control Register (ECSPIx_CONREG)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210129132323.30946-7-bmeng.cn@gmail.com
Message-Id: <20210115153049.3353008-6-f4bug@amsat.org>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/ssi/imx_spi.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index 21e2c9dea3e..4cfbb73e35e 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -332,6 +332,14 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
     DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index),
             (uint32_t)value);
 
+    if (!imx_spi_is_enabled(s)) {
+        /* Block is disabled */
+        if (index != ECSPI_CONREG) {
+            /* Ignore access */
+            return;
+        }
+    }
+
     change_mask = s->regs[index] ^ value;
 
     switch (index) {
@@ -340,10 +348,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
                       TYPE_IMX_SPI, __func__);
         break;
     case ECSPI_TXDATA:
-        if (!imx_spi_is_enabled(s)) {
-            /* Ignore writes if device is disabled */
-            break;
-        } else if (fifo32_is_full(&s->tx_fifo)) {
+        if (fifo32_is_full(&s->tx_fifo)) {
             /* Ignore writes if queue is full */
             break;
         }
-- 
2.20.1



  parent reply	other threads:[~2021-02-02 18:19 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-02 17:54 [PULL 00/21] target-arm queue Peter Maydell
2021-02-02 17:54 ` [PULL 01/21] hw/intc/arm_gic: Allow to use QTest without crashing Peter Maydell
2021-02-02 17:54 ` [PULL 02/21] hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled Peter Maydell
2021-02-02 17:54 ` [PULL 03/21] hw/char/exynos4210_uart: Fix missing call to report ready for input Peter Maydell
2021-02-02 17:55 ` [PULL 04/21] hw/arm/smmuv3: Fix addr_mask for range-based invalidation Peter Maydell
2021-02-02 17:55 ` [PULL 05/21] hw/ssi: imx_spi: Use a macro for number of chip selects supported Peter Maydell
2021-02-02 17:55 ` [PULL 06/21] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() Peter Maydell
2021-02-02 17:55 ` [PULL 07/21] hw/ssi: imx_spi: Remove pointless variable initialization Peter Maydell
2021-02-02 17:55 ` [PULL 08/21] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Peter Maydell
2021-02-02 17:55 ` [PULL 09/21] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Peter Maydell
2021-02-02 17:55 ` Peter Maydell [this message]
2021-02-02 17:55 ` [PULL 11/21] hw/ssi: imx_spi: Disable chip selects when controller is disabled Peter Maydell
2021-02-02 17:55 ` [PULL 12/21] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Peter Maydell
2021-02-02 17:55 ` [PULL 13/21] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Peter Maydell
2021-02-02 17:55 ` [PULL 14/21] hw/ssi: imx_spi: Correct tx and rx fifo endianness Peter Maydell
2021-02-02 17:55 ` [PULL 15/21] hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register Peter Maydell
2021-02-02 17:55 ` [PULL 16/21] hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ Peter Maydell
2021-02-02 17:55 ` [PULL 17/21] hw/arm/exynos4210: " Peter Maydell
2021-02-02 17:55 ` [PULL 18/21] hw/arm/xlnx-versal: Versal SoC requires ZDMA Peter Maydell
2021-02-02 17:55 ` [PULL 19/21] hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals Peter Maydell
2021-02-02 17:55 ` [PULL 20/21] hw/net/can: ZynqMP CAN device requires PTIMER Peter Maydell
2021-02-02 17:55 ` [PULL 21/21] hw/arm: Display CPU type in machine description Peter Maydell
2021-02-03  9:22 ` [PULL 00/21] target-arm queue Philippe Mathieu-Daudé
2021-02-03 10:12   ` P J P

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