From: Claudio Fontana <cfontana@suse.de>
To: "Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Roman Bolshakov <r.bolshakov@yadro.com>,
Claudio Fontana <cfontana@suse.de>,
Eduardo Habkost <ehabkost@redhat.com>,
qemu-devel@nongnu.org
Subject: [RFC v12 21/65] target/arm: split vfp state setting from tcg helpers
Date: Fri, 26 Mar 2021 20:36:17 +0100 [thread overview]
Message-ID: <20210326193701.5981-22-cfontana@suse.de> (raw)
In-Reply-To: <20210326193701.5981-1-cfontana@suse.de>
cpu-vfp.c: vfp_get_fpsr and vfp_set_fpsr are needed also for KVM,
so create a new cpu-vfp.c
tcg/cpu-vfp.c: vfp_get_fpscr_from_host and vv are TCG-only, so we
move the implementation to tcg/cpu-vfp.c
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/arm/cpu-vfp.h | 29 +++++
target/arm/cpu-vfp.c | 97 +++++++++++++++++
target/arm/tcg/cpu-vfp.c | 146 +++++++++++++++++++++++++
target/arm/tcg/vfp_helper.c | 210 +-----------------------------------
target/arm/meson.build | 1 +
target/arm/tcg/meson.build | 1 +
6 files changed, 276 insertions(+), 208 deletions(-)
create mode 100644 target/arm/cpu-vfp.h
create mode 100644 target/arm/cpu-vfp.c
create mode 100644 target/arm/tcg/cpu-vfp.c
diff --git a/target/arm/cpu-vfp.h b/target/arm/cpu-vfp.h
new file mode 100644
index 0000000000..41e0d710a0
--- /dev/null
+++ b/target/arm/cpu-vfp.h
@@ -0,0 +1,29 @@
+/*
+ * ARM VFP floating-point operations internals
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CPU_VFP_H
+#define CPU_VFP_H
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+
+uint32_t vfp_get_fpscr_from_host(CPUARMState *env);
+void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val);
+
+#endif /* CPU_VFP_H */
diff --git a/target/arm/cpu-vfp.c b/target/arm/cpu-vfp.c
new file mode 100644
index 0000000000..8ea615a916
--- /dev/null
+++ b/target/arm/cpu-vfp.c
@@ -0,0 +1,97 @@
+/*
+ * ARM VFP floating-point operations
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "cpu-vfp.h"
+#include "sysemu/tcg.h"
+
+uint32_t vfp_get_fpscr(CPUARMState *env)
+{
+ uint32_t i, fpscr;
+
+ fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
+ | (env->vfp.vec_len << 16)
+ | (env->vfp.vec_stride << 20);
+
+ /*
+ * M-profile LTPSIZE overlaps A-profile Stride; whichever of the
+ * two is not applicable to this CPU will always be zero.
+ */
+ fpscr |= env->v7m.ltpsize << 16;
+
+ if (tcg_enabled()) {
+ fpscr |= vfp_get_fpscr_from_host(env);
+ }
+
+ i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
+ fpscr |= i ? FPCR_QC : 0;
+
+ return fpscr;
+}
+
+void vfp_set_fpscr(CPUARMState *env, uint32_t val)
+{
+ /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
+ if (!cpu_isar_feature(any_fp16, env_archcpu(env))) {
+ val &= ~FPCR_FZ16;
+ }
+
+ if (tcg_enabled()) {
+ vfp_set_fpscr_to_host(env, val);
+ }
+
+ if (!arm_feature(env, ARM_FEATURE_M)) {
+ /*
+ * Short-vector length and stride; on M-profile these bits
+ * are used for different purposes.
+ * We can't make this conditional be "if MVFR0.FPShVec != 0",
+ * because in v7A no-short-vector-support cores still had to
+ * allow Stride/Len to be written with the only effect that
+ * some insns are required to UNDEF if the guest sets them.
+ *
+ * TODO: if M-profile MVE implemented, set LTPSIZE.
+ */
+ env->vfp.vec_len = extract32(val, 16, 3);
+ env->vfp.vec_stride = extract32(val, 20, 2);
+ }
+
+ if (arm_feature(env, ARM_FEATURE_NEON)) {
+ /*
+ * The bit we set within fpscr_q is arbitrary; the register as a
+ * whole being zero/non-zero is what counts.
+ * TODO: M-profile MVE also has a QC bit.
+ */
+ env->vfp.qc[0] = val & FPCR_QC;
+ env->vfp.qc[1] = 0;
+ env->vfp.qc[2] = 0;
+ env->vfp.qc[3] = 0;
+ }
+
+ /*
+ * We don't implement trapped exception handling, so the
+ * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
+ *
+ * The exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in
+ * fp_status; QC, Len and Stride are stored separately earlier.
+ * Clear out all of those and the RES0 bits: only NZCV, AHP, DN,
+ * FZ, RMode and FZ16 are kept in vfp.xregs[FPSCR].
+ */
+ env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
+}
diff --git a/target/arm/tcg/cpu-vfp.c b/target/arm/tcg/cpu-vfp.c
new file mode 100644
index 0000000000..bb88abf1ba
--- /dev/null
+++ b/target/arm/tcg/cpu-vfp.c
@@ -0,0 +1,146 @@
+/*
+ * ARM VFP floating-point operations
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "qemu/log.h"
+#include "internals.h"
+#include "fpu/softfloat.h"
+#include "cpu-vfp.h"
+
+/* Convert host exception flags to vfp form. */
+static inline int vfp_exceptbits_from_host(int host_bits)
+{
+ int target_bits = 0;
+
+ if (host_bits & float_flag_invalid) {
+ target_bits |= 1;
+ }
+ if (host_bits & float_flag_divbyzero) {
+ target_bits |= 2;
+ }
+ if (host_bits & float_flag_overflow) {
+ target_bits |= 4;
+ }
+ if (host_bits & (float_flag_underflow | float_flag_output_denormal)) {
+ target_bits |= 8;
+ }
+ if (host_bits & float_flag_inexact) {
+ target_bits |= 0x10;
+ }
+ if (host_bits & float_flag_input_denormal) {
+ target_bits |= 0x80;
+ }
+ return target_bits;
+}
+
+/* Convert vfp exception flags to target form. */
+static inline int vfp_exceptbits_to_host(int target_bits)
+{
+ int host_bits = 0;
+
+ if (target_bits & 1) {
+ host_bits |= float_flag_invalid;
+ }
+ if (target_bits & 2) {
+ host_bits |= float_flag_divbyzero;
+ }
+ if (target_bits & 4) {
+ host_bits |= float_flag_overflow;
+ }
+ if (target_bits & 8) {
+ host_bits |= float_flag_underflow;
+ }
+ if (target_bits & 0x10) {
+ host_bits |= float_flag_inexact;
+ }
+ if (target_bits & 0x80) {
+ host_bits |= float_flag_input_denormal;
+ }
+ return host_bits;
+}
+
+uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
+{
+ uint32_t i;
+
+ i = get_float_exception_flags(&env->vfp.fp_status);
+ i |= get_float_exception_flags(&env->vfp.standard_fp_status);
+ /* FZ16 does not generate an input denormal exception. */
+ i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
+ & ~float_flag_input_denormal);
+ i |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16)
+ & ~float_flag_input_denormal);
+ return vfp_exceptbits_from_host(i);
+}
+
+void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
+{
+ int i;
+ uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];
+
+ changed ^= val;
+ if (changed & (3 << 22)) {
+ i = (val >> 22) & 3;
+ switch (i) {
+ case FPROUNDING_TIEEVEN:
+ i = float_round_nearest_even;
+ break;
+ case FPROUNDING_POSINF:
+ i = float_round_up;
+ break;
+ case FPROUNDING_NEGINF:
+ i = float_round_down;
+ break;
+ case FPROUNDING_ZERO:
+ i = float_round_to_zero;
+ break;
+ }
+ set_float_rounding_mode(i, &env->vfp.fp_status);
+ set_float_rounding_mode(i, &env->vfp.fp_status_f16);
+ }
+ if (changed & FPCR_FZ16) {
+ bool ftz_enabled = val & FPCR_FZ16;
+ set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
+ set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
+ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
+ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
+ }
+ if (changed & FPCR_FZ) {
+ bool ftz_enabled = val & FPCR_FZ;
+ set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
+ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
+ }
+ if (changed & FPCR_DN) {
+ bool dnan_enabled = val & FPCR_DN;
+ set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
+ set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
+ }
+
+ /*
+ * The exception flags are ORed together when we read fpscr so we
+ * only need to preserve the current state in one of our
+ * float_status values.
+ */
+ i = vfp_exceptbits_to_host(val);
+ set_float_exception_flags(i, &env->vfp.fp_status);
+ set_float_exception_flags(0, &env->vfp.fp_status_f16);
+ set_float_exception_flags(0, &env->vfp.standard_fp_status);
+ set_float_exception_flags(0, &env->vfp.standard_fp_status_f16);
+}
diff --git a/target/arm/tcg/vfp_helper.c b/target/arm/tcg/vfp_helper.c
index 01b9d8557f..521719f327 100644
--- a/target/arm/tcg/vfp_helper.c
+++ b/target/arm/tcg/vfp_helper.c
@@ -30,220 +30,14 @@
Single precision routines have a "s" suffix, double precision a
"d" suffix. */
-#ifdef CONFIG_TCG
-
-/* Convert host exception flags to vfp form. */
-static inline int vfp_exceptbits_from_host(int host_bits)
-{
- int target_bits = 0;
-
- if (host_bits & float_flag_invalid) {
- target_bits |= 1;
- }
- if (host_bits & float_flag_divbyzero) {
- target_bits |= 2;
- }
- if (host_bits & float_flag_overflow) {
- target_bits |= 4;
- }
- if (host_bits & (float_flag_underflow | float_flag_output_denormal)) {
- target_bits |= 8;
- }
- if (host_bits & float_flag_inexact) {
- target_bits |= 0x10;
- }
- if (host_bits & float_flag_input_denormal) {
- target_bits |= 0x80;
- }
- return target_bits;
-}
-
-/* Convert vfp exception flags to target form. */
-static inline int vfp_exceptbits_to_host(int target_bits)
-{
- int host_bits = 0;
-
- if (target_bits & 1) {
- host_bits |= float_flag_invalid;
- }
- if (target_bits & 2) {
- host_bits |= float_flag_divbyzero;
- }
- if (target_bits & 4) {
- host_bits |= float_flag_overflow;
- }
- if (target_bits & 8) {
- host_bits |= float_flag_underflow;
- }
- if (target_bits & 0x10) {
- host_bits |= float_flag_inexact;
- }
- if (target_bits & 0x80) {
- host_bits |= float_flag_input_denormal;
- }
- return host_bits;
-}
-
-static uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
-{
- uint32_t i;
-
- i = get_float_exception_flags(&env->vfp.fp_status);
- i |= get_float_exception_flags(&env->vfp.standard_fp_status);
- /* FZ16 does not generate an input denormal exception. */
- i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
- & ~float_flag_input_denormal);
- i |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16)
- & ~float_flag_input_denormal);
- return vfp_exceptbits_from_host(i);
-}
-
-static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
-{
- int i;
- uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];
-
- changed ^= val;
- if (changed & (3 << 22)) {
- i = (val >> 22) & 3;
- switch (i) {
- case FPROUNDING_TIEEVEN:
- i = float_round_nearest_even;
- break;
- case FPROUNDING_POSINF:
- i = float_round_up;
- break;
- case FPROUNDING_NEGINF:
- i = float_round_down;
- break;
- case FPROUNDING_ZERO:
- i = float_round_to_zero;
- break;
- }
- set_float_rounding_mode(i, &env->vfp.fp_status);
- set_float_rounding_mode(i, &env->vfp.fp_status_f16);
- }
- if (changed & FPCR_FZ16) {
- bool ftz_enabled = val & FPCR_FZ16;
- set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
- set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
- set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
- set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
- }
- if (changed & FPCR_FZ) {
- bool ftz_enabled = val & FPCR_FZ;
- set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
- set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
- }
- if (changed & FPCR_DN) {
- bool dnan_enabled = val & FPCR_DN;
- set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
- set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
- }
-
- /*
- * The exception flags are ORed together when we read fpscr so we
- * only need to preserve the current state in one of our
- * float_status values.
- */
- i = vfp_exceptbits_to_host(val);
- set_float_exception_flags(i, &env->vfp.fp_status);
- set_float_exception_flags(0, &env->vfp.fp_status_f16);
- set_float_exception_flags(0, &env->vfp.standard_fp_status);
- set_float_exception_flags(0, &env->vfp.standard_fp_status_f16);
-}
-
-#else
-
-static uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
-{
- return 0;
-}
-
-static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
-{
-}
-
-#endif
-
uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
{
- uint32_t i, fpscr;
-
- fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
- | (env->vfp.vec_len << 16)
- | (env->vfp.vec_stride << 20);
-
- /*
- * M-profile LTPSIZE overlaps A-profile Stride; whichever of the
- * two is not applicable to this CPU will always be zero.
- */
- fpscr |= env->v7m.ltpsize << 16;
-
- fpscr |= vfp_get_fpscr_from_host(env);
-
- i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
- fpscr |= i ? FPCR_QC : 0;
-
- return fpscr;
-}
-
-uint32_t vfp_get_fpscr(CPUARMState *env)
-{
- return HELPER(vfp_get_fpscr)(env);
+ return vfp_get_fpscr(env);
}
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
{
- /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
- if (!cpu_isar_feature(any_fp16, env_archcpu(env))) {
- val &= ~FPCR_FZ16;
- }
-
- vfp_set_fpscr_to_host(env, val);
-
- if (!arm_feature(env, ARM_FEATURE_M)) {
- /*
- * Short-vector length and stride; on M-profile these bits
- * are used for different purposes.
- * We can't make this conditional be "if MVFR0.FPShVec != 0",
- * because in v7A no-short-vector-support cores still had to
- * allow Stride/Len to be written with the only effect that
- * some insns are required to UNDEF if the guest sets them.
- *
- * TODO: if M-profile MVE implemented, set LTPSIZE.
- */
- env->vfp.vec_len = extract32(val, 16, 3);
- env->vfp.vec_stride = extract32(val, 20, 2);
- }
-
- if (arm_feature(env, ARM_FEATURE_NEON)) {
- /*
- * The bit we set within fpscr_q is arbitrary; the register as a
- * whole being zero/non-zero is what counts.
- * TODO: M-profile MVE also has a QC bit.
- */
- env->vfp.qc[0] = val & FPCR_QC;
- env->vfp.qc[1] = 0;
- env->vfp.qc[2] = 0;
- env->vfp.qc[3] = 0;
- }
-
- /*
- * We don't implement trapped exception handling, so the
- * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
- *
- * The exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in
- * fp_status; QC, Len and Stride are stored separately earlier.
- * Clear out all of those and the RES0 bits: only NZCV, AHP, DN,
- * FZ, RMode and FZ16 are kept in vfp.xregs[FPSCR].
- */
- env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
-}
-
-void vfp_set_fpscr(CPUARMState *env, uint32_t val)
-{
- HELPER(vfp_set_fpscr)(env, val);
+ vfp_set_fpscr(env, val);
}
#ifdef CONFIG_TCG
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 1f7375375e..4bc44e1db2 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -4,6 +4,7 @@ arm_ss.add(files(
'cpu.c',
'cpu-common.c',
'cpu-mmu.c',
+ 'cpu-vfp.c',
'cpustate-list.c',
'gdbstub.c',
'cpu_tcg.c',
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index a0ef03a6e3..f77e2ccf01 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -18,6 +18,7 @@ arm_ss.add(when: 'CONFIG_TCG', if_true: files(
'translate.c',
'helper.c',
'cpregs.c',
+ 'cpu-vfp.c',
'iwmmxt_helper.c',
'm_helper.c',
'neon_helper.c',
--
2.26.2
next prev parent reply other threads:[~2021-03-26 19:57 UTC|newest]
Thread overview: 145+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-26 19:35 [RFC v12 00/65] arm cleanup experiment for kvm-only build Claudio Fontana
2021-03-26 19:35 ` [RFC v12 01/65] target/arm: move translate modules to tcg/ Claudio Fontana
2021-03-26 19:35 ` [RFC v12 02/65] target/arm: move helpers " Claudio Fontana
2021-03-26 19:35 ` [RFC v12 03/65] arm: tcg: only build under CONFIG_TCG Claudio Fontana
2021-04-13 20:49 ` Philippe Mathieu-Daudé
2021-04-14 8:28 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 04/65] target/arm: tcg: add sysemu and user subdirs Claudio Fontana
2021-03-28 15:42 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 05/65] target/arm: tcg: split mte_helper user-only and sysemu code Claudio Fontana
2021-04-08 14:41 ` Alex Bennée
2021-04-08 15:56 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 06/65] target/arm: tcg: move sysemu-only parts of debug_helper Claudio Fontana
2021-04-08 14:47 ` Alex Bennée
2021-03-26 19:36 ` [RFC v12 07/65] target/arm: tcg: split tlb_helper user-only and sysemu-only parts Claudio Fontana
2021-04-08 14:20 ` Alex Bennée
2021-03-26 19:36 ` [RFC v12 08/65] target/arm: tcg: split m_helper " Claudio Fontana
2021-04-08 17:34 ` Alex Bennée
2021-03-26 19:36 ` [RFC v12 09/65] target/arm: only build psci for TCG Claudio Fontana
2021-03-28 15:43 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 10/65] target/arm: split off cpu-sysemu.c Claudio Fontana
2021-03-26 19:36 ` [RFC v12 11/65] target/arm: tcg: fix comment style before move to cpu-mmu Claudio Fontana
2021-03-28 15:44 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 12/65] target/arm: move physical address translation " Claudio Fontana
2021-04-12 14:13 ` Alex Bennée
2021-03-26 19:36 ` [RFC v12 13/65] target/arm: fix style in preparation of new cpregs module Claudio Fontana
2021-03-28 15:45 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 14/65] target/arm: split cpregs from tcg/helper.c Claudio Fontana
2021-03-28 15:49 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 15/65] target/arm: move cpu definitions to common cpu module Claudio Fontana
2021-03-26 19:36 ` [RFC v12 16/65] target/arm: only perform TCG cpu and machine inits if TCG enabled Claudio Fontana
2021-03-26 19:36 ` [RFC v12 17/65] target/arm: tcg: add stubs for some helpers for non-tcg builds Claudio Fontana
2021-03-28 15:51 ` Richard Henderson
2021-03-28 16:22 ` Richard Henderson
2021-04-08 10:39 ` Claudio Fontana
2021-04-08 14:35 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 18/65] target/arm: move cpsr_read, cpsr_write to cpu_common Claudio Fontana
2021-03-28 15:54 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 19/65] target/arm: add temporary stub for arm_rebuild_hflags Claudio Fontana
2021-03-28 15:57 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 20/65] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu Claudio Fontana
2021-03-28 16:05 ` Richard Henderson
2021-03-26 19:36 ` Claudio Fontana [this message]
2021-03-28 16:10 ` [RFC v12 21/65] target/arm: split vfp state setting from tcg helpers Richard Henderson
2021-03-26 19:36 ` [RFC v12 22/65] target/arm: move arm_mmu_idx* to cpu-mmu Claudio Fontana
2021-03-26 19:36 ` [RFC v12 23/65] target/arm: move sve_zcr_len_for_el to common_cpu Claudio Fontana
2021-03-26 19:36 ` [RFC v12 24/65] target/arm: move arm_sctlr away from tcg helpers Claudio Fontana
2021-03-28 16:12 ` Richard Henderson
2021-04-08 9:55 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 25/65] target/arm: move arm_cpu_list to common_cpu Claudio Fontana
2021-03-26 19:36 ` [RFC v12 26/65] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code Claudio Fontana
2021-03-26 19:36 ` [RFC v12 27/65] target/arm: split a15 cpu model and 32bit class functions to cpu32.c Claudio Fontana
2021-03-28 16:18 ` Richard Henderson
2021-04-08 10:23 ` Claudio Fontana
2021-04-08 10:36 ` Peter Maydell
2021-04-12 9:05 ` Claudio Fontana
2021-04-12 9:10 ` Peter Maydell
2021-04-13 8:32 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 28/65] target/arm: fixup sve_exception_el code style before move Claudio Fontana
2021-03-28 16:19 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 29/65] target/arm: move sve_exception_el out of TCG helpers Claudio Fontana
2021-03-26 19:36 ` [RFC v12 30/65] target/arm: fix style of arm_cpu_do_interrupt functions before move Claudio Fontana
2021-03-28 16:24 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 31/65] target/arm: move exception code out of tcg/helper.c Claudio Fontana
2021-03-28 16:40 ` Richard Henderson
2021-04-08 10:56 ` Claudio Fontana
2021-04-08 15:05 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 32/65] target/arm: move TCGCPUOps to tcg/tcg-cpu.c Claudio Fontana
2021-03-28 16:48 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 33/65] target/arm: move cpu_tcg to tcg/tcg-cpu-models.c Claudio Fontana
2021-03-28 16:52 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 34/65] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Claudio Fontana
2021-03-26 19:36 ` [RFC v12 35/65] target/arm: remove kvm include file for PSCI and arm-powerctl Claudio Fontana
2021-03-26 19:36 ` [RFC v12 36/65] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/ Claudio Fontana
2021-03-28 16:54 ` Richard Henderson
2021-03-28 16:56 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 37/65] target/arm: cleanup cpu includes Claudio Fontana
2021-03-28 16:58 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 38/65] target/arm: remove broad "else" statements when checking accels Claudio Fontana
2021-03-28 17:11 ` Richard Henderson
2021-03-29 6:58 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 39/65] target/arm: remove kvm-stub.c Claudio Fontana
2021-03-28 17:12 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 40/65] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM Claudio Fontana
2021-03-28 17:21 ` Richard Henderson
2021-03-29 7:02 ` Claudio Fontana
2021-03-29 14:03 ` Richard Henderson
2021-04-08 13:24 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 41/65] tests: restrict TCG-only arm-cpu-features tests to TCG builds Claudio Fontana
2021-03-28 17:23 ` Richard Henderson
2021-04-08 13:30 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 42/65] tests: do not run test-hmp on all machines for ARM KVM-only Claudio Fontana
2021-03-28 17:24 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 43/65] tests: device-introspect-test: cope with ARM TCG-only devices Claudio Fontana
2021-03-28 17:25 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 44/65] tests: do not run qom-test on all machines for ARM KVM-only Claudio Fontana
2021-03-28 17:26 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 45/65] Revert "target/arm: Restrict v8M IDAU to TCG" Claudio Fontana
2021-03-28 17:40 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 46/65] target/arm: create kvm cpu accel class Claudio Fontana
2021-03-28 17:46 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 47/65] target/arm: move kvm post init initialization to kvm cpu accel Claudio Fontana
2021-03-28 17:49 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 48/65] target/arm: add tcg cpu accel class Claudio Fontana
2021-03-28 17:51 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 49/65] target/arm: move TCG gt timer creation code in tcg/ Claudio Fontana
2021-03-28 17:54 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 50/65] target/arm: cpu-sve: new module Claudio Fontana
2021-03-28 18:05 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 51/65] target/arm: cpu-sve: split TCG and KVM functionality Claudio Fontana
2021-03-28 18:21 ` Richard Henderson
2021-04-08 14:28 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 52/65] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 Claudio Fontana
2021-03-28 18:31 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 53/65] target/arm: restrict rebuild_hflags_a64 to TARGET_AARCH64 Claudio Fontana
2021-03-28 18:34 ` Richard Henderson
2021-03-28 19:02 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 54/65] target/arm: arch_dump: restrict ELFCLASS64 to AArch64 Claudio Fontana
2021-03-28 18:36 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 55/65] target/arm: cpu-exceptions: new module Claudio Fontana
2021-03-28 18:40 ` Richard Henderson
2021-04-12 11:53 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 56/65] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64 Claudio Fontana
2021-03-28 18:47 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 57/65] target/arm: tcg-sve: import narrow_vq and change_el functions Claudio Fontana
2021-03-28 18:51 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 58/65] target/arm: tcg-sve: rename the " Claudio Fontana
2021-03-28 18:55 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 59/65] target/arm: move sve_zcr_len_for_el to TARGET_AARCH64-only cpu-sve Claudio Fontana
2021-03-28 19:03 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 60/65] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication Claudio Fontana
2021-03-28 19:05 ` Richard Henderson
2021-04-13 12:16 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 61/65] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el Claudio Fontana
2021-03-28 19:09 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 62/65] target/arm: refactor arm_cpu_finalize_features into cpu64 Claudio Fontana
2021-03-28 19:12 ` Richard Henderson
2021-03-28 19:15 ` Richard Henderson
2021-04-13 17:14 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 63/65] XXX target/arm: experiment refactoring cpu "max" Claudio Fontana
2021-03-26 19:37 ` [RFC v12 64/65] target/arm: tcg: remove superfluous CONFIG_TCG check Claudio Fontana
2021-03-28 19:16 ` Richard Henderson
2021-03-26 19:37 ` [RFC v12 65/65] target/arm: remove v7m stub function for !CONFIG_TCG Claudio Fontana
2021-03-28 19:17 ` Richard Henderson
2021-03-28 19:27 ` [RFC v12 00/65] arm cleanup experiment for kvm-only build Richard Henderson
2021-04-13 12:05 ` Claudio Fontana
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