From: Claudio Fontana <cfontana@suse.de>
To: "Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Roman Bolshakov <r.bolshakov@yadro.com>,
Claudio Fontana <cfontana@suse.de>,
Eduardo Habkost <ehabkost@redhat.com>,
qemu-devel@nongnu.org
Subject: [RFC v12 57/65] target/arm: tcg-sve: import narrow_vq and change_el functions
Date: Fri, 26 Mar 2021 20:36:53 +0100 [thread overview]
Message-ID: <20210326193701.5981-58-cfontana@suse.de> (raw)
In-Reply-To: <20210326193701.5981-1-cfontana@suse.de>
aarch64_sve_narrow_vq and aarch64_sve_change_el are SVE-related
functions only used for TCG, so we can put them in the
tcg-sve.c module.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/arm/cpu.h | 7 ---
target/arm/tcg/tcg-sve.h | 7 +++
linux-user/syscall.c | 4 ++
target/arm/cpu-exceptions-aa64.c | 1 +
target/arm/tcg/cpregs.c | 4 ++
target/arm/tcg/helper-a64.c | 1 +
target/arm/tcg/helper.c | 87 --------------------------------
target/arm/tcg/tcg-sve.c | 86 +++++++++++++++++++++++++++++++
8 files changed, 103 insertions(+), 94 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index fd740e1940..6917c8161d 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1049,9 +1049,6 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
#ifdef TARGET_AARCH64
int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
-void aarch64_sve_change_el(CPUARMState *env, int old_el,
- int new_el, bool el0_a64);
static inline bool is_a64(CPUARMState *env)
{
@@ -1083,10 +1080,6 @@ static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
}
#else
-static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
-static inline void aarch64_sve_change_el(CPUARMState *env, int o,
- int n, bool a)
-{ }
#define is_a64(env) (false)
diff --git a/target/arm/tcg/tcg-sve.h b/target/arm/tcg/tcg-sve.h
index 4bed809b9a..289c1936e1 100644
--- a/target/arm/tcg/tcg-sve.h
+++ b/target/arm/tcg/tcg-sve.h
@@ -21,4 +21,11 @@ uint32_t tcg_sve_disable_lens(unsigned long *sve_vq_map,
bool tcg_sve_validate_lens(unsigned long *sve_vq_map, uint32_t max_vq,
Error **errp);
+/* tcg/helper.c */
+
+void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
+
+void aarch64_sve_change_el(CPUARMState *env, int old_el,
+ int new_el, bool el0_a64);
+
#endif /* TCG_SVE_H */
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 1e508576c7..a271a81d34 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -134,6 +134,10 @@
#include "fd-trans.h"
#include "tcg/tcg.h"
+#ifdef TARGET_AARCH64
+#include "tcg/tcg-sve.h"
+#endif /* TARGET_AARCH64 */
+
#ifndef CLONE_IO
#define CLONE_IO 0x80000000 /* Clone io context */
#endif
diff --git a/target/arm/cpu-exceptions-aa64.c b/target/arm/cpu-exceptions-aa64.c
index dec4549841..b80f5a99de 100644
--- a/target/arm/cpu-exceptions-aa64.c
+++ b/target/arm/cpu-exceptions-aa64.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "cpu.h"
+#include "tcg/tcg-sve.h"
#include "internals.h"
#include "sysemu/tcg.h"
diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c
index d72832aeaa..0a99490a50 100644
--- a/target/arm/tcg/cpregs.c
+++ b/target/arm/tcg/cpregs.c
@@ -16,6 +16,10 @@
#include "cpu-mmu.h"
#include "cpregs.h"
+#ifdef TARGET_AARCH64
+#include "tcg/tcg-sve.h"
+#endif /* TARGET_AARCH64 */
+
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
#define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index b75ce80473..65d7c24578 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "cpu.h"
+#include "tcg/tcg-sve.h"
#include "cpu-exceptions-aa64.h"
#include "exec/gdbstub.h"
#include "exec/helper-proto.h"
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index 6fc037b132..2c0cc115f2 100644
--- a/target/arm/tcg/helper.c
+++ b/target/arm/tcg/helper.c
@@ -1379,90 +1379,3 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
*pflags = flags;
}
-
-#ifdef TARGET_AARCH64
-/*
- * The manual says that when SVE is enabled and VQ is widened the
- * implementation is allowed to zero the previously inaccessible
- * portion of the registers. The corollary to that is that when
- * SVE is enabled and VQ is narrowed we are also allowed to zero
- * the now inaccessible portion of the registers.
- *
- * The intent of this is that no predicate bit beyond VQ is ever set.
- * Which means that some operations on predicate registers themselves
- * may operate on full uint64_t or even unrolled across the maximum
- * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
- * may well be cheaper than conditionals to restrict the operation
- * to the relevant portion of a uint16_t[16].
- */
-void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
-{
- int i, j;
- uint64_t pmask;
-
- assert(vq >= 1 && vq <= ARM_MAX_VQ);
- assert(vq <= env_archcpu(env)->sve_max_vq);
-
- /* Zap the high bits of the zregs. */
- for (i = 0; i < 32; i++) {
- memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq));
- }
-
- /* Zap the high bits of the pregs and ffr. */
- pmask = 0;
- if (vq & 3) {
- pmask = ~(-1ULL << (16 * (vq & 3)));
- }
- for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) {
- for (i = 0; i < 17; ++i) {
- env->vfp.pregs[i].p[j] &= pmask;
- }
- pmask = 0;
- }
-}
-
-/*
- * Notice a change in SVE vector size when changing EL.
- */
-void aarch64_sve_change_el(CPUARMState *env, int old_el,
- int new_el, bool el0_a64)
-{
- ARMCPU *cpu = env_archcpu(env);
- int old_len, new_len;
- bool old_a64, new_a64;
-
- /* Nothing to do if no SVE. */
- if (!cpu_isar_feature(aa64_sve, cpu)) {
- return;
- }
-
- /* Nothing to do if FP is disabled in either EL. */
- if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) {
- return;
- }
-
- /*
- * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
- * at ELx, or not available because the EL is in AArch32 state, then
- * for all purposes other than a direct read, the ZCR_ELx.LEN field
- * has an effective value of 0".
- *
- * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
- * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
- * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
- * we already have the correct register contents when encountering the
- * vq0->vq0 transition between EL0->EL1.
- */
- old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64;
- old_len = (old_a64 && !sve_exception_el(env, old_el)
- ? sve_zcr_len_for_el(env, old_el) : 0);
- new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64;
- new_len = (new_a64 && !sve_exception_el(env, new_el)
- ? sve_zcr_len_for_el(env, new_el) : 0);
-
- /* When changing vector length, clear inaccessible state. */
- if (new_len < old_len) {
- aarch64_sve_narrow_vq(env, new_len + 1);
- }
-}
-#endif
diff --git a/target/arm/tcg/tcg-sve.c b/target/arm/tcg/tcg-sve.c
index 99cfde1f41..908d2c2f2c 100644
--- a/target/arm/tcg/tcg-sve.c
+++ b/target/arm/tcg/tcg-sve.c
@@ -24,6 +24,7 @@
#include "sysemu/tcg.h"
#include "cpu-sve.h"
#include "tcg-sve.h"
+#include "cpu-exceptions-aa64.h"
void tcg_sve_enable_lens(unsigned long *sve_vq_map,
unsigned long *sve_vq_init, uint32_t max_vq)
@@ -79,3 +80,88 @@ bool tcg_sve_validate_lens(unsigned long *sve_vq_map, uint32_t max_vq,
}
return true;
}
+
+/*
+ * The manual says that when SVE is enabled and VQ is widened the
+ * implementation is allowed to zero the previously inaccessible
+ * portion of the registers. The corollary to that is that when
+ * SVE is enabled and VQ is narrowed we are also allowed to zero
+ * the now inaccessible portion of the registers.
+ *
+ * The intent of this is that no predicate bit beyond VQ is ever set.
+ * Which means that some operations on predicate registers themselves
+ * may operate on full uint64_t or even unrolled across the maximum
+ * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
+ * may well be cheaper than conditionals to restrict the operation
+ * to the relevant portion of a uint16_t[16].
+ */
+void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
+{
+ int i, j;
+ uint64_t pmask;
+
+ assert(vq >= 1 && vq <= ARM_MAX_VQ);
+ assert(vq <= env_archcpu(env)->sve_max_vq);
+
+ /* Zap the high bits of the zregs. */
+ for (i = 0; i < 32; i++) {
+ memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq));
+ }
+
+ /* Zap the high bits of the pregs and ffr. */
+ pmask = 0;
+ if (vq & 3) {
+ pmask = ~(-1ULL << (16 * (vq & 3)));
+ }
+ for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) {
+ for (i = 0; i < 17; ++i) {
+ env->vfp.pregs[i].p[j] &= pmask;
+ }
+ pmask = 0;
+ }
+}
+
+/*
+ * Notice a change in SVE vector size when changing EL.
+ */
+void aarch64_sve_change_el(CPUARMState *env, int old_el,
+ int new_el, bool el0_a64)
+{
+ ARMCPU *cpu = env_archcpu(env);
+ int old_len, new_len;
+ bool old_a64, new_a64;
+
+ /* Nothing to do if no SVE. */
+ if (!cpu_isar_feature(aa64_sve, cpu)) {
+ return;
+ }
+
+ /* Nothing to do if FP is disabled in either EL. */
+ if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) {
+ return;
+ }
+
+ /*
+ * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
+ * at ELx, or not available because the EL is in AArch32 state, then
+ * for all purposes other than a direct read, the ZCR_ELx.LEN field
+ * has an effective value of 0".
+ *
+ * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
+ * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
+ * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
+ * we already have the correct register contents when encountering the
+ * vq0->vq0 transition between EL0->EL1.
+ */
+ old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64;
+ old_len = (old_a64 && !sve_exception_el(env, old_el)
+ ? sve_zcr_len_for_el(env, old_el) : 0);
+ new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64;
+ new_len = (new_a64 && !sve_exception_el(env, new_el)
+ ? sve_zcr_len_for_el(env, new_el) : 0);
+
+ /* When changing vector length, clear inaccessible state. */
+ if (new_len < old_len) {
+ aarch64_sve_narrow_vq(env, new_len + 1);
+ }
+}
--
2.26.2
next prev parent reply other threads:[~2021-03-26 20:37 UTC|newest]
Thread overview: 145+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-26 19:35 [RFC v12 00/65] arm cleanup experiment for kvm-only build Claudio Fontana
2021-03-26 19:35 ` [RFC v12 01/65] target/arm: move translate modules to tcg/ Claudio Fontana
2021-03-26 19:35 ` [RFC v12 02/65] target/arm: move helpers " Claudio Fontana
2021-03-26 19:35 ` [RFC v12 03/65] arm: tcg: only build under CONFIG_TCG Claudio Fontana
2021-04-13 20:49 ` Philippe Mathieu-Daudé
2021-04-14 8:28 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 04/65] target/arm: tcg: add sysemu and user subdirs Claudio Fontana
2021-03-28 15:42 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 05/65] target/arm: tcg: split mte_helper user-only and sysemu code Claudio Fontana
2021-04-08 14:41 ` Alex Bennée
2021-04-08 15:56 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 06/65] target/arm: tcg: move sysemu-only parts of debug_helper Claudio Fontana
2021-04-08 14:47 ` Alex Bennée
2021-03-26 19:36 ` [RFC v12 07/65] target/arm: tcg: split tlb_helper user-only and sysemu-only parts Claudio Fontana
2021-04-08 14:20 ` Alex Bennée
2021-03-26 19:36 ` [RFC v12 08/65] target/arm: tcg: split m_helper " Claudio Fontana
2021-04-08 17:34 ` Alex Bennée
2021-03-26 19:36 ` [RFC v12 09/65] target/arm: only build psci for TCG Claudio Fontana
2021-03-28 15:43 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 10/65] target/arm: split off cpu-sysemu.c Claudio Fontana
2021-03-26 19:36 ` [RFC v12 11/65] target/arm: tcg: fix comment style before move to cpu-mmu Claudio Fontana
2021-03-28 15:44 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 12/65] target/arm: move physical address translation " Claudio Fontana
2021-04-12 14:13 ` Alex Bennée
2021-03-26 19:36 ` [RFC v12 13/65] target/arm: fix style in preparation of new cpregs module Claudio Fontana
2021-03-28 15:45 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 14/65] target/arm: split cpregs from tcg/helper.c Claudio Fontana
2021-03-28 15:49 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 15/65] target/arm: move cpu definitions to common cpu module Claudio Fontana
2021-03-26 19:36 ` [RFC v12 16/65] target/arm: only perform TCG cpu and machine inits if TCG enabled Claudio Fontana
2021-03-26 19:36 ` [RFC v12 17/65] target/arm: tcg: add stubs for some helpers for non-tcg builds Claudio Fontana
2021-03-28 15:51 ` Richard Henderson
2021-03-28 16:22 ` Richard Henderson
2021-04-08 10:39 ` Claudio Fontana
2021-04-08 14:35 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 18/65] target/arm: move cpsr_read, cpsr_write to cpu_common Claudio Fontana
2021-03-28 15:54 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 19/65] target/arm: add temporary stub for arm_rebuild_hflags Claudio Fontana
2021-03-28 15:57 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 20/65] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu Claudio Fontana
2021-03-28 16:05 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 21/65] target/arm: split vfp state setting from tcg helpers Claudio Fontana
2021-03-28 16:10 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 22/65] target/arm: move arm_mmu_idx* to cpu-mmu Claudio Fontana
2021-03-26 19:36 ` [RFC v12 23/65] target/arm: move sve_zcr_len_for_el to common_cpu Claudio Fontana
2021-03-26 19:36 ` [RFC v12 24/65] target/arm: move arm_sctlr away from tcg helpers Claudio Fontana
2021-03-28 16:12 ` Richard Henderson
2021-04-08 9:55 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 25/65] target/arm: move arm_cpu_list to common_cpu Claudio Fontana
2021-03-26 19:36 ` [RFC v12 26/65] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code Claudio Fontana
2021-03-26 19:36 ` [RFC v12 27/65] target/arm: split a15 cpu model and 32bit class functions to cpu32.c Claudio Fontana
2021-03-28 16:18 ` Richard Henderson
2021-04-08 10:23 ` Claudio Fontana
2021-04-08 10:36 ` Peter Maydell
2021-04-12 9:05 ` Claudio Fontana
2021-04-12 9:10 ` Peter Maydell
2021-04-13 8:32 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 28/65] target/arm: fixup sve_exception_el code style before move Claudio Fontana
2021-03-28 16:19 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 29/65] target/arm: move sve_exception_el out of TCG helpers Claudio Fontana
2021-03-26 19:36 ` [RFC v12 30/65] target/arm: fix style of arm_cpu_do_interrupt functions before move Claudio Fontana
2021-03-28 16:24 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 31/65] target/arm: move exception code out of tcg/helper.c Claudio Fontana
2021-03-28 16:40 ` Richard Henderson
2021-04-08 10:56 ` Claudio Fontana
2021-04-08 15:05 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 32/65] target/arm: move TCGCPUOps to tcg/tcg-cpu.c Claudio Fontana
2021-03-28 16:48 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 33/65] target/arm: move cpu_tcg to tcg/tcg-cpu-models.c Claudio Fontana
2021-03-28 16:52 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 34/65] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Claudio Fontana
2021-03-26 19:36 ` [RFC v12 35/65] target/arm: remove kvm include file for PSCI and arm-powerctl Claudio Fontana
2021-03-26 19:36 ` [RFC v12 36/65] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/ Claudio Fontana
2021-03-28 16:54 ` Richard Henderson
2021-03-28 16:56 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 37/65] target/arm: cleanup cpu includes Claudio Fontana
2021-03-28 16:58 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 38/65] target/arm: remove broad "else" statements when checking accels Claudio Fontana
2021-03-28 17:11 ` Richard Henderson
2021-03-29 6:58 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 39/65] target/arm: remove kvm-stub.c Claudio Fontana
2021-03-28 17:12 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 40/65] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM Claudio Fontana
2021-03-28 17:21 ` Richard Henderson
2021-03-29 7:02 ` Claudio Fontana
2021-03-29 14:03 ` Richard Henderson
2021-04-08 13:24 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 41/65] tests: restrict TCG-only arm-cpu-features tests to TCG builds Claudio Fontana
2021-03-28 17:23 ` Richard Henderson
2021-04-08 13:30 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 42/65] tests: do not run test-hmp on all machines for ARM KVM-only Claudio Fontana
2021-03-28 17:24 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 43/65] tests: device-introspect-test: cope with ARM TCG-only devices Claudio Fontana
2021-03-28 17:25 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 44/65] tests: do not run qom-test on all machines for ARM KVM-only Claudio Fontana
2021-03-28 17:26 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 45/65] Revert "target/arm: Restrict v8M IDAU to TCG" Claudio Fontana
2021-03-28 17:40 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 46/65] target/arm: create kvm cpu accel class Claudio Fontana
2021-03-28 17:46 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 47/65] target/arm: move kvm post init initialization to kvm cpu accel Claudio Fontana
2021-03-28 17:49 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 48/65] target/arm: add tcg cpu accel class Claudio Fontana
2021-03-28 17:51 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 49/65] target/arm: move TCG gt timer creation code in tcg/ Claudio Fontana
2021-03-28 17:54 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 50/65] target/arm: cpu-sve: new module Claudio Fontana
2021-03-28 18:05 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 51/65] target/arm: cpu-sve: split TCG and KVM functionality Claudio Fontana
2021-03-28 18:21 ` Richard Henderson
2021-04-08 14:28 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 52/65] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 Claudio Fontana
2021-03-28 18:31 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 53/65] target/arm: restrict rebuild_hflags_a64 to TARGET_AARCH64 Claudio Fontana
2021-03-28 18:34 ` Richard Henderson
2021-03-28 19:02 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 54/65] target/arm: arch_dump: restrict ELFCLASS64 to AArch64 Claudio Fontana
2021-03-28 18:36 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 55/65] target/arm: cpu-exceptions: new module Claudio Fontana
2021-03-28 18:40 ` Richard Henderson
2021-04-12 11:53 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 56/65] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64 Claudio Fontana
2021-03-28 18:47 ` Richard Henderson
2021-03-26 19:36 ` Claudio Fontana [this message]
2021-03-28 18:51 ` [RFC v12 57/65] target/arm: tcg-sve: import narrow_vq and change_el functions Richard Henderson
2021-03-26 19:36 ` [RFC v12 58/65] target/arm: tcg-sve: rename the " Claudio Fontana
2021-03-28 18:55 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 59/65] target/arm: move sve_zcr_len_for_el to TARGET_AARCH64-only cpu-sve Claudio Fontana
2021-03-28 19:03 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 60/65] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication Claudio Fontana
2021-03-28 19:05 ` Richard Henderson
2021-04-13 12:16 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 61/65] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el Claudio Fontana
2021-03-28 19:09 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 62/65] target/arm: refactor arm_cpu_finalize_features into cpu64 Claudio Fontana
2021-03-28 19:12 ` Richard Henderson
2021-03-28 19:15 ` Richard Henderson
2021-04-13 17:14 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 63/65] XXX target/arm: experiment refactoring cpu "max" Claudio Fontana
2021-03-26 19:37 ` [RFC v12 64/65] target/arm: tcg: remove superfluous CONFIG_TCG check Claudio Fontana
2021-03-28 19:16 ` Richard Henderson
2021-03-26 19:37 ` [RFC v12 65/65] target/arm: remove v7m stub function for !CONFIG_TCG Claudio Fontana
2021-03-28 19:17 ` Richard Henderson
2021-03-28 19:27 ` [RFC v12 00/65] arm cleanup experiment for kvm-only build Richard Henderson
2021-04-13 12:05 ` Claudio Fontana
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