From: Claudio Fontana <cfontana@suse.de>
To: "Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Roman Bolshakov <r.bolshakov@yadro.com>,
Claudio Fontana <cfontana@suse.de>,
Eduardo Habkost <ehabkost@redhat.com>,
qemu-devel@nongnu.org
Subject: [RFC v12 48/65] target/arm: add tcg cpu accel class
Date: Fri, 26 Mar 2021 20:36:44 +0100 [thread overview]
Message-ID: <20210326193701.5981-49-cfontana@suse.de> (raw)
In-Reply-To: <20210326193701.5981-1-cfontana@suse.de>
move init, realizefn and reset code into it.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Cc: Paolo Bonzini <pbonzini@redhat.com>
---
target/arm/tcg/tcg-cpu.h | 4 ++-
target/arm/cpu.c | 44 ++------------------------
target/arm/tcg/sysemu/tcg-cpu.c | 27 ++++++++++++++++
target/arm/tcg/tcg-cpu-models.c | 10 +++---
target/arm/tcg/tcg-cpu.c | 55 +++++++++++++++++++++++++++++++--
5 files changed, 92 insertions(+), 48 deletions(-)
diff --git a/target/arm/tcg/tcg-cpu.h b/target/arm/tcg/tcg-cpu.h
index d93c6a6749..dd08587949 100644
--- a/target/arm/tcg/tcg-cpu.h
+++ b/target/arm/tcg/tcg-cpu.h
@@ -22,15 +22,17 @@
#include "cpu.h"
#include "hw/core/tcg-cpu-ops.h"
+#include "hw/core/accel-cpu.h"
void arm_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb);
-extern struct TCGCPUOps arm_tcg_ops;
+void tcg_arm_init_accel_cpu(AccelCPUClass *accel_cpu, CPUClass *cc);
#ifndef CONFIG_USER_ONLY
/* Do semihosting call and set the appropriate return value. */
void tcg_handle_semihosting(CPUState *cs);
+bool tcg_cpu_realizefn(CPUState *cs, Error **errp);
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5e0f6bd01d..9248e096df 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -410,12 +410,6 @@ static void arm_cpu_reset(DeviceState *dev)
&env->vfp.fp_status_f16);
set_float_detect_tininess(float_tininess_before_rounding,
&env->vfp.standard_fp_status_f16);
-
- if (tcg_enabled()) {
- hw_breakpoint_update_all(cpu);
- hw_watchpoint_update_all(cpu);
- arm_rebuild_hflags(env);
- }
}
void arm_cpu_update_virq(ARMCPU *cpu)
@@ -576,10 +570,6 @@ static void arm_cpu_initfn(Object *obj)
cpu->dtb_compatible = "qemu,unknown";
cpu->psci_version = 1; /* By default assume PSCI v0.1 */
cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
-
- if (tcg_enabled()) {
- cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
- }
}
static Property arm_cpu_gt_cntfrq_property =
@@ -868,34 +858,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
Error *local_err = NULL;
bool no_aa32 = false;
- /*
- * If we needed to query the host kernel for the CPU features
- * then it's possible that might have failed in the initfn, but
- * this is the first point where we can report it.
- */
- if (cpu->host_cpu_probe_failed) {
- error_setg(errp, "The 'host' CPU type can only be used with KVM");
- return;
- }
-
-#ifndef CONFIG_USER_ONLY
- /* The NVIC and M-profile CPU are two halves of a single piece of
- * hardware; trying to use one without the other is a command line
- * error and will result in segfaults if not caught here.
- */
- if (arm_feature(env, ARM_FEATURE_M)) {
- if (!env->nvic) {
- error_setg(errp, "This board cannot be used with Cortex-M CPUs");
- return;
- }
- } else {
- if (env->nvic) {
- error_setg(errp, "This board can only be used with Cortex-M CPUs");
- return;
- }
- }
-
-#ifdef CONFIG_TCG
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
{
uint64_t scale;
@@ -921,8 +884,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
arm_gt_hvtimer_cb, cpu);
}
-#endif /* CONFIG_TCG */
-#endif /* !CONFIG_USER_ONLY */
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
@@ -1458,7 +1420,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = arm_disas_set_info;
#ifdef CONFIG_TCG
- cc->tcg_ops = &arm_tcg_ops;
+ cc->init_accel_cpu = tcg_arm_init_accel_cpu;
#endif /* CONFIG_TCG */
arm32_cpu_class_init(oc, data);
diff --git a/target/arm/tcg/sysemu/tcg-cpu.c b/target/arm/tcg/sysemu/tcg-cpu.c
index 327b2a5073..115ac523dc 100644
--- a/target/arm/tcg/sysemu/tcg-cpu.c
+++ b/target/arm/tcg/sysemu/tcg-cpu.c
@@ -19,10 +19,13 @@
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/timer.h"
#include "cpu.h"
#include "semihosting/common-semi.h"
#include "qemu/log.h"
#include "tcg/tcg-cpu.h"
+#include "internals.h"
/*
* Do semihosting call and set the appropriate return value. All the
@@ -50,3 +53,27 @@ void tcg_handle_semihosting(CPUState *cs)
env->regs[15] += env->thumb ? 2 : 4;
}
}
+
+bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
+ /*
+ * The NVIC and M-profile CPU are two halves of a single piece of
+ * hardware; trying to use one without the other is a command line
+ * error and will result in segfaults if not caught here.
+ */
+ if (arm_feature(env, ARM_FEATURE_M)) {
+ if (!env->nvic) {
+ error_setg(errp, "This board cannot be used with Cortex-M CPUs");
+ return false;
+ }
+ } else {
+ if (env->nvic) {
+ error_setg(errp, "This board can only be used with Cortex-M CPUs");
+ return false;
+ }
+ }
+ return true;
+}
diff --git a/target/arm/tcg/tcg-cpu-models.c b/target/arm/tcg/tcg-cpu-models.c
index 840e284f47..720df5d26b 100644
--- a/target/arm/tcg/tcg-cpu-models.c
+++ b/target/arm/tcg/tcg-cpu-models.c
@@ -843,16 +843,18 @@ static struct TCGCPUOps arm_v7m_tcg_ops = {
#endif /* !CONFIG_USER_ONLY */
};
+static void arm_v7m_init_accel_cpu(AccelCPUClass *accel_cpu, CPUClass *cc)
+{
+ cc->tcg_ops = &arm_v7m_tcg_ops;
+}
+
static void arm_v7m_class_init(ObjectClass *oc, void *data)
{
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
acc->info = data;
-#ifdef CONFIG_TCG
- cc->tcg_ops = &arm_v7m_tcg_ops;
-#endif /* CONFIG_TCG */
-
+ cc->init_accel_cpu = arm_v7m_init_accel_cpu;
cc->gdb_core_xml_file = "arm-m-profile.xml";
}
diff --git a/target/arm/tcg/tcg-cpu.c b/target/arm/tcg/tcg-cpu.c
index 9fd996d908..db677bc71c 100644
--- a/target/arm/tcg/tcg-cpu.c
+++ b/target/arm/tcg/tcg-cpu.c
@@ -20,8 +20,8 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "qapi/error.h"
#include "tcg-cpu.h"
-#include "hw/core/tcg-cpu-ops.h"
#include "cpregs.h"
#include "internals.h"
#include "exec/exec-all.h"
@@ -212,7 +212,7 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return true;
}
-struct TCGCPUOps arm_tcg_ops = {
+static struct TCGCPUOps arm_tcg_ops = {
.initialize = arm_translate_init,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
.cpu_exec_interrupt = arm_cpu_exec_interrupt,
@@ -227,3 +227,54 @@ struct TCGCPUOps arm_tcg_ops = {
.debug_check_watchpoint = arm_debug_check_watchpoint,
#endif /* !CONFIG_USER_ONLY */
};
+
+static void tcg_cpu_instance_init(CPUState *cs)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+
+ /*
+ * this would be the place to move TCG-specific props
+ * in future refactoring of cpu properties.
+ */
+
+ cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
+}
+
+static void tcg_cpu_reset(CPUState *cs)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
+ hw_breakpoint_update_all(cpu);
+ hw_watchpoint_update_all(cpu);
+ arm_rebuild_hflags(env);
+}
+
+void tcg_arm_init_accel_cpu(AccelCPUClass *accel_cpu, CPUClass *cc)
+{
+ cc->tcg_ops = &arm_tcg_ops;
+}
+
+static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
+{
+ AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
+
+#ifndef CONFIG_USER_ONLY
+ acc->cpu_realizefn = tcg_cpu_realizefn;
+#endif /* CONFIG_USER_ONLY */
+
+ acc->cpu_instance_init = tcg_cpu_instance_init;
+ acc->cpu_reset = tcg_cpu_reset;
+}
+static const TypeInfo tcg_cpu_accel_type_info = {
+ .name = ACCEL_CPU_NAME("tcg"),
+
+ .parent = TYPE_ACCEL_CPU,
+ .class_init = tcg_cpu_accel_class_init,
+ .abstract = true,
+};
+static void tcg_cpu_accel_register_types(void)
+{
+ type_register_static(&tcg_cpu_accel_type_info);
+}
+type_init(tcg_cpu_accel_register_types);
--
2.26.2
next prev parent reply other threads:[~2021-03-26 20:23 UTC|newest]
Thread overview: 145+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-26 19:35 [RFC v12 00/65] arm cleanup experiment for kvm-only build Claudio Fontana
2021-03-26 19:35 ` [RFC v12 01/65] target/arm: move translate modules to tcg/ Claudio Fontana
2021-03-26 19:35 ` [RFC v12 02/65] target/arm: move helpers " Claudio Fontana
2021-03-26 19:35 ` [RFC v12 03/65] arm: tcg: only build under CONFIG_TCG Claudio Fontana
2021-04-13 20:49 ` Philippe Mathieu-Daudé
2021-04-14 8:28 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 04/65] target/arm: tcg: add sysemu and user subdirs Claudio Fontana
2021-03-28 15:42 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 05/65] target/arm: tcg: split mte_helper user-only and sysemu code Claudio Fontana
2021-04-08 14:41 ` Alex Bennée
2021-04-08 15:56 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 06/65] target/arm: tcg: move sysemu-only parts of debug_helper Claudio Fontana
2021-04-08 14:47 ` Alex Bennée
2021-03-26 19:36 ` [RFC v12 07/65] target/arm: tcg: split tlb_helper user-only and sysemu-only parts Claudio Fontana
2021-04-08 14:20 ` Alex Bennée
2021-03-26 19:36 ` [RFC v12 08/65] target/arm: tcg: split m_helper " Claudio Fontana
2021-04-08 17:34 ` Alex Bennée
2021-03-26 19:36 ` [RFC v12 09/65] target/arm: only build psci for TCG Claudio Fontana
2021-03-28 15:43 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 10/65] target/arm: split off cpu-sysemu.c Claudio Fontana
2021-03-26 19:36 ` [RFC v12 11/65] target/arm: tcg: fix comment style before move to cpu-mmu Claudio Fontana
2021-03-28 15:44 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 12/65] target/arm: move physical address translation " Claudio Fontana
2021-04-12 14:13 ` Alex Bennée
2021-03-26 19:36 ` [RFC v12 13/65] target/arm: fix style in preparation of new cpregs module Claudio Fontana
2021-03-28 15:45 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 14/65] target/arm: split cpregs from tcg/helper.c Claudio Fontana
2021-03-28 15:49 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 15/65] target/arm: move cpu definitions to common cpu module Claudio Fontana
2021-03-26 19:36 ` [RFC v12 16/65] target/arm: only perform TCG cpu and machine inits if TCG enabled Claudio Fontana
2021-03-26 19:36 ` [RFC v12 17/65] target/arm: tcg: add stubs for some helpers for non-tcg builds Claudio Fontana
2021-03-28 15:51 ` Richard Henderson
2021-03-28 16:22 ` Richard Henderson
2021-04-08 10:39 ` Claudio Fontana
2021-04-08 14:35 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 18/65] target/arm: move cpsr_read, cpsr_write to cpu_common Claudio Fontana
2021-03-28 15:54 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 19/65] target/arm: add temporary stub for arm_rebuild_hflags Claudio Fontana
2021-03-28 15:57 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 20/65] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu Claudio Fontana
2021-03-28 16:05 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 21/65] target/arm: split vfp state setting from tcg helpers Claudio Fontana
2021-03-28 16:10 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 22/65] target/arm: move arm_mmu_idx* to cpu-mmu Claudio Fontana
2021-03-26 19:36 ` [RFC v12 23/65] target/arm: move sve_zcr_len_for_el to common_cpu Claudio Fontana
2021-03-26 19:36 ` [RFC v12 24/65] target/arm: move arm_sctlr away from tcg helpers Claudio Fontana
2021-03-28 16:12 ` Richard Henderson
2021-04-08 9:55 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 25/65] target/arm: move arm_cpu_list to common_cpu Claudio Fontana
2021-03-26 19:36 ` [RFC v12 26/65] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code Claudio Fontana
2021-03-26 19:36 ` [RFC v12 27/65] target/arm: split a15 cpu model and 32bit class functions to cpu32.c Claudio Fontana
2021-03-28 16:18 ` Richard Henderson
2021-04-08 10:23 ` Claudio Fontana
2021-04-08 10:36 ` Peter Maydell
2021-04-12 9:05 ` Claudio Fontana
2021-04-12 9:10 ` Peter Maydell
2021-04-13 8:32 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 28/65] target/arm: fixup sve_exception_el code style before move Claudio Fontana
2021-03-28 16:19 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 29/65] target/arm: move sve_exception_el out of TCG helpers Claudio Fontana
2021-03-26 19:36 ` [RFC v12 30/65] target/arm: fix style of arm_cpu_do_interrupt functions before move Claudio Fontana
2021-03-28 16:24 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 31/65] target/arm: move exception code out of tcg/helper.c Claudio Fontana
2021-03-28 16:40 ` Richard Henderson
2021-04-08 10:56 ` Claudio Fontana
2021-04-08 15:05 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 32/65] target/arm: move TCGCPUOps to tcg/tcg-cpu.c Claudio Fontana
2021-03-28 16:48 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 33/65] target/arm: move cpu_tcg to tcg/tcg-cpu-models.c Claudio Fontana
2021-03-28 16:52 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 34/65] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Claudio Fontana
2021-03-26 19:36 ` [RFC v12 35/65] target/arm: remove kvm include file for PSCI and arm-powerctl Claudio Fontana
2021-03-26 19:36 ` [RFC v12 36/65] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/ Claudio Fontana
2021-03-28 16:54 ` Richard Henderson
2021-03-28 16:56 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 37/65] target/arm: cleanup cpu includes Claudio Fontana
2021-03-28 16:58 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 38/65] target/arm: remove broad "else" statements when checking accels Claudio Fontana
2021-03-28 17:11 ` Richard Henderson
2021-03-29 6:58 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 39/65] target/arm: remove kvm-stub.c Claudio Fontana
2021-03-28 17:12 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 40/65] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM Claudio Fontana
2021-03-28 17:21 ` Richard Henderson
2021-03-29 7:02 ` Claudio Fontana
2021-03-29 14:03 ` Richard Henderson
2021-04-08 13:24 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 41/65] tests: restrict TCG-only arm-cpu-features tests to TCG builds Claudio Fontana
2021-03-28 17:23 ` Richard Henderson
2021-04-08 13:30 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 42/65] tests: do not run test-hmp on all machines for ARM KVM-only Claudio Fontana
2021-03-28 17:24 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 43/65] tests: device-introspect-test: cope with ARM TCG-only devices Claudio Fontana
2021-03-28 17:25 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 44/65] tests: do not run qom-test on all machines for ARM KVM-only Claudio Fontana
2021-03-28 17:26 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 45/65] Revert "target/arm: Restrict v8M IDAU to TCG" Claudio Fontana
2021-03-28 17:40 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 46/65] target/arm: create kvm cpu accel class Claudio Fontana
2021-03-28 17:46 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 47/65] target/arm: move kvm post init initialization to kvm cpu accel Claudio Fontana
2021-03-28 17:49 ` Richard Henderson
2021-03-26 19:36 ` Claudio Fontana [this message]
2021-03-28 17:51 ` [RFC v12 48/65] target/arm: add tcg cpu accel class Richard Henderson
2021-03-26 19:36 ` [RFC v12 49/65] target/arm: move TCG gt timer creation code in tcg/ Claudio Fontana
2021-03-28 17:54 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 50/65] target/arm: cpu-sve: new module Claudio Fontana
2021-03-28 18:05 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 51/65] target/arm: cpu-sve: split TCG and KVM functionality Claudio Fontana
2021-03-28 18:21 ` Richard Henderson
2021-04-08 14:28 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 52/65] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 Claudio Fontana
2021-03-28 18:31 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 53/65] target/arm: restrict rebuild_hflags_a64 to TARGET_AARCH64 Claudio Fontana
2021-03-28 18:34 ` Richard Henderson
2021-03-28 19:02 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 54/65] target/arm: arch_dump: restrict ELFCLASS64 to AArch64 Claudio Fontana
2021-03-28 18:36 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 55/65] target/arm: cpu-exceptions: new module Claudio Fontana
2021-03-28 18:40 ` Richard Henderson
2021-04-12 11:53 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 56/65] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64 Claudio Fontana
2021-03-28 18:47 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 57/65] target/arm: tcg-sve: import narrow_vq and change_el functions Claudio Fontana
2021-03-28 18:51 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 58/65] target/arm: tcg-sve: rename the " Claudio Fontana
2021-03-28 18:55 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 59/65] target/arm: move sve_zcr_len_for_el to TARGET_AARCH64-only cpu-sve Claudio Fontana
2021-03-28 19:03 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 60/65] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication Claudio Fontana
2021-03-28 19:05 ` Richard Henderson
2021-04-13 12:16 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 61/65] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el Claudio Fontana
2021-03-28 19:09 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 62/65] target/arm: refactor arm_cpu_finalize_features into cpu64 Claudio Fontana
2021-03-28 19:12 ` Richard Henderson
2021-03-28 19:15 ` Richard Henderson
2021-04-13 17:14 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 63/65] XXX target/arm: experiment refactoring cpu "max" Claudio Fontana
2021-03-26 19:37 ` [RFC v12 64/65] target/arm: tcg: remove superfluous CONFIG_TCG check Claudio Fontana
2021-03-28 19:16 ` Richard Henderson
2021-03-26 19:37 ` [RFC v12 65/65] target/arm: remove v7m stub function for !CONFIG_TCG Claudio Fontana
2021-03-28 19:17 ` Richard Henderson
2021-03-28 19:27 ` [RFC v12 00/65] arm cleanup experiment for kvm-only build Richard Henderson
2021-04-13 12:05 ` Claudio Fontana
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