From: Claudio Fontana <cfontana@suse.de>
To: "Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Roman Bolshakov <r.bolshakov@yadro.com>,
Claudio Fontana <cfontana@suse.de>,
Eduardo Habkost <ehabkost@redhat.com>,
qemu-devel@nongnu.org
Subject: [RFC v14 20/80] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu
Date: Fri, 16 Apr 2021 18:27:24 +0200 [thread overview]
Message-ID: <20210416162824.25131-21-cfontana@suse.de> (raw)
In-Reply-To: <20210416162824.25131-1-cfontana@suse.de>
we will need this for KVM too, especially for Nested support.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu-common.c | 68 +++++++++++++++++++++++++++++++++++++++++
target/arm/tcg/helper.c | 68 -----------------------------------------
2 files changed, 68 insertions(+), 68 deletions(-)
diff --git a/target/arm/cpu-common.c b/target/arm/cpu-common.c
index 694e5d73f3..040e06392a 100644
--- a/target/arm/cpu-common.c
+++ b/target/arm/cpu-common.c
@@ -231,3 +231,71 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
mask &= ~CACHED_CPSR_BITS;
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
}
+
+/*
+ * Return the effective value of HCR_EL2.
+ * Bits that are not included here:
+ * RW (read from SCR_EL3.RW as needed)
+ */
+uint64_t arm_hcr_el2_eff(CPUARMState *env)
+{
+ uint64_t ret = env->cp15.hcr_el2;
+
+ if (!arm_is_el2_enabled(env)) {
+ /*
+ * "This register has no effect if EL2 is not enabled in the
+ * current Security state". This is ARMv8.4-SecEL2 speak for
+ * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
+ *
+ * Prior to that, the language was "In an implementation that
+ * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
+ * as if this field is 0 for all purposes other than a direct
+ * read or write access of HCR_EL2". With lots of enumeration
+ * on a per-field basis. In current QEMU, this is condition
+ * is arm_is_secure_below_el3.
+ *
+ * Since the v8.4 language applies to the entire register, and
+ * appears to be backward compatible, use that.
+ */
+ return 0;
+ }
+
+ /*
+ * For a cpu that supports both aarch64 and aarch32, we can set bits
+ * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
+ * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
+ */
+ if (!arm_el_is_aa64(env, 2)) {
+ uint64_t aa32_valid;
+
+ /*
+ * These bits are up-to-date as of ARMv8.6.
+ * For HCR, it's easiest to list just the 2 bits that are invalid.
+ * For HCR2, list those that are valid.
+ */
+ aa32_valid = MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ);
+ aa32_valid |= (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNCE |
+ HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS);
+ ret &= aa32_valid;
+ }
+
+ if (ret & HCR_TGE) {
+ /* These bits are up-to-date as of ARMv8.6. */
+ if (ret & HCR_E2H) {
+ ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO |
+ HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE |
+ HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU |
+ HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE |
+ HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT |
+ HCR_TTLBIS | HCR_TTLBOS | HCR_TID5);
+ } else {
+ ret |= HCR_FMO | HCR_IMO | HCR_AMO;
+ }
+ ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE |
+ HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR |
+ HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM |
+ HCR_TLOR);
+ }
+
+ return ret;
+}
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index f35d2969b0..15f53d57b0 100644
--- a/target/arm/tcg/helper.c
+++ b/target/arm/tcg/helper.c
@@ -261,74 +261,6 @@ static int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
}
#endif /* TARGET_AARCH64 */
-/*
- * Return the effective value of HCR_EL2.
- * Bits that are not included here:
- * RW (read from SCR_EL3.RW as needed)
- */
-uint64_t arm_hcr_el2_eff(CPUARMState *env)
-{
- uint64_t ret = env->cp15.hcr_el2;
-
- if (!arm_is_el2_enabled(env)) {
- /*
- * "This register has no effect if EL2 is not enabled in the
- * current Security state". This is ARMv8.4-SecEL2 speak for
- * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
- *
- * Prior to that, the language was "In an implementation that
- * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
- * as if this field is 0 for all purposes other than a direct
- * read or write access of HCR_EL2". With lots of enumeration
- * on a per-field basis. In current QEMU, this is condition
- * is arm_is_secure_below_el3.
- *
- * Since the v8.4 language applies to the entire register, and
- * appears to be backward compatible, use that.
- */
- return 0;
- }
-
- /*
- * For a cpu that supports both aarch64 and aarch32, we can set bits
- * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
- * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
- */
- if (!arm_el_is_aa64(env, 2)) {
- uint64_t aa32_valid;
-
- /*
- * These bits are up-to-date as of ARMv8.6.
- * For HCR, it's easiest to list just the 2 bits that are invalid.
- * For HCR2, list those that are valid.
- */
- aa32_valid = MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ);
- aa32_valid |= (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNCE |
- HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS);
- ret &= aa32_valid;
- }
-
- if (ret & HCR_TGE) {
- /* These bits are up-to-date as of ARMv8.6. */
- if (ret & HCR_E2H) {
- ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO |
- HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE |
- HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU |
- HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE |
- HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT |
- HCR_TTLBIS | HCR_TTLBOS | HCR_TID5);
- } else {
- ret |= HCR_FMO | HCR_IMO | HCR_AMO;
- }
- ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE |
- HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR |
- HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM |
- HCR_TLOR);
- }
-
- return ret;
-}
-
/* Return the exception level to which exceptions should be taken
* via SVEAccessTrap. If an exception should be routed through
* AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
--
2.26.2
next prev parent reply other threads:[~2021-04-16 16:56 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-16 16:27 [RFC v14 00/80] arm cleanup experiment for kvm-only build Claudio Fontana
2021-04-16 16:27 ` [RFC v14 01/80] target/arm: move translate modules to tcg/ Claudio Fontana
2021-04-16 16:27 ` [RFC v14 02/80] target/arm: move helpers " Claudio Fontana
2021-04-16 16:27 ` [RFC v14 03/80] arm: tcg: only build under CONFIG_TCG Claudio Fontana
2021-04-16 16:27 ` [RFC v14 04/80] target/arm: tcg: add sysemu and user subdirs Claudio Fontana
2021-04-20 9:53 ` Alex Bennée
2021-04-16 16:27 ` [RFC v14 05/80] target/arm: tcg: split mte_helper user-only and sysemu code Claudio Fontana
2021-04-16 16:27 ` [RFC v14 06/80] target/arm: tcg: move sysemu-only parts of debug_helper Claudio Fontana
2021-04-16 16:27 ` [RFC v14 07/80] target/arm: tcg: split tlb_helper user-only and sysemu-only parts Claudio Fontana
2021-04-16 16:27 ` [RFC v14 08/80] target/arm: tcg: split m_helper " Claudio Fontana
2021-04-16 16:27 ` [RFC v14 09/80] target/arm: only build psci for TCG Claudio Fontana
2021-04-20 10:28 ` Alex Bennée
2021-04-16 16:27 ` [RFC v14 10/80] target/arm: split off cpu-sysemu.c Claudio Fontana
2021-04-16 16:27 ` [RFC v14 11/80] target/arm: tcg: fix comment style before move to cpu-mmu Claudio Fontana
2021-04-20 10:30 ` Alex Bennée
2021-04-16 16:27 ` [RFC v14 12/80] target/arm: move physical address translation " Claudio Fontana
2021-04-16 16:27 ` [RFC v14 13/80] target/arm: fix style in preparation of new cpregs module Claudio Fontana
2021-04-20 10:33 ` Alex Bennée
2021-04-16 16:27 ` [RFC v14 14/80] target/arm: split cpregs from tcg/helper.c Claudio Fontana
2021-04-20 10:56 ` Alex Bennée
2021-04-16 16:27 ` [RFC v14 15/80] target/arm: move cpu definitions to common cpu module Claudio Fontana
2021-04-20 10:57 ` Alex Bennée
2021-04-16 16:27 ` [RFC v14 16/80] target/arm: only perform TCG cpu and machine inits if TCG enabled Claudio Fontana
2021-04-16 16:27 ` [RFC v14 17/80] target/arm: tcg: add stubs for some helpers for non-tcg builds Claudio Fontana
2021-04-16 16:27 ` [RFC v14 18/80] target/arm: move cpsr_read, cpsr_write to cpu_common Claudio Fontana
2021-04-16 16:27 ` [RFC v14 19/80] target/arm: add temporary stub for arm_rebuild_hflags Claudio Fontana
2021-04-16 16:27 ` Claudio Fontana [this message]
2021-04-16 16:27 ` [RFC v14 21/80] target/arm: split vfp state setting from tcg helpers Claudio Fontana
2021-04-16 16:27 ` [RFC v14 22/80] target/arm: move arm_mmu_idx* to cpu-mmu Claudio Fontana
2021-04-16 16:27 ` [RFC v14 23/80] target/arm: move sve_zcr_len_for_el to common_cpu Claudio Fontana
2021-04-16 16:27 ` [RFC v14 24/80] target/arm: move arm_sctlr away from tcg helpers Claudio Fontana
2021-04-16 16:27 ` [RFC v14 25/80] target/arm: move arm_cpu_list to common_cpu Claudio Fontana
2021-04-16 16:27 ` [RFC v14 26/80] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code Claudio Fontana
2021-04-16 16:27 ` [RFC v14 27/80] target/arm: new cpu32 ARM 32 bit CPU Class Claudio Fontana
2021-04-16 16:27 ` [RFC v14 28/80] target/arm: split 32bit and 64bit arm dump state Claudio Fontana
2021-04-16 16:27 ` [RFC v14 29/80] target/arm: move a15 cpu model away from the TCG-only models Claudio Fontana
2021-04-16 16:27 ` [RFC v14 30/80] target/arm: fixup sve_exception_el code style before move Claudio Fontana
2021-04-16 16:27 ` [RFC v14 31/80] target/arm: move sve_exception_el out of TCG helpers Claudio Fontana
2021-04-16 16:27 ` [RFC v14 32/80] target/arm: fix comments style of fp_exception_el before moving it Claudio Fontana
2021-04-16 16:27 ` [RFC v14 33/80] target/arm: move fp_exception_el out of TCG helpers Claudio Fontana
2021-04-16 16:27 ` [RFC v14 34/80] target/arm: remove now useless ifndef from fp_exception_el Claudio Fontana
2021-04-16 16:27 ` [RFC v14 35/80] target/arm: make further preparation for the exception code to move Claudio Fontana
2021-04-16 16:27 ` [RFC v14 36/80] target/arm: fix style of arm_cpu_do_interrupt functions before move Claudio Fontana
2021-04-16 16:27 ` [RFC v14 37/80] target/arm: move exception code out of tcg/helper.c Claudio Fontana
2021-04-16 16:27 ` [RFC v14 38/80] target/arm: rename handle_semihosting to tcg_handle_semihosting Claudio Fontana
2021-04-16 16:27 ` [RFC v14 39/80] target/arm: replace CONFIG_TCG with tcg_enabled Claudio Fontana
2021-04-16 16:27 ` [RFC v14 40/80] target/arm: move TCGCPUOps to tcg/tcg-cpu.c Claudio Fontana
2021-04-16 16:27 ` [RFC v14 41/80] target/arm: move cpu_tcg to tcg/tcg-cpu-models.c Claudio Fontana
2021-04-16 16:27 ` [RFC v14 42/80] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Claudio Fontana
2021-04-16 16:27 ` [RFC v14 43/80] target/arm: remove kvm include file for PSCI and arm-powerctl Claudio Fontana
2021-04-16 16:27 ` [RFC v14 44/80] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/ Claudio Fontana
2021-04-16 16:27 ` [RFC v14 45/80] MAINTAINERS: update arm kvm maintained files to all in target/arm/kvm/ Claudio Fontana
2021-04-16 16:27 ` [RFC v14 46/80] target/arm: cleanup cpu includes Claudio Fontana
2021-04-16 16:27 ` [RFC v14 47/80] target/arm: remove broad "else" statements when checking accels Claudio Fontana
2021-04-16 16:27 ` [RFC v14 48/80] target/arm: remove kvm-stub.c Claudio Fontana
2021-04-16 16:27 ` [RFC v14 49/80] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM Claudio Fontana
2021-04-16 16:27 ` [RFC v14 50/80] tests: restrict TCG-only arm-cpu-features tests to TCG builds Claudio Fontana
2021-04-16 16:27 ` [RFC v14 51/80] tests: do not run test-hmp on all machines for ARM KVM-only Claudio Fontana
2021-04-16 16:27 ` [RFC v14 52/80] tests: device-introspect-test: cope with ARM TCG-only devices Claudio Fontana
2021-04-19 10:22 ` Thomas Huth
2021-04-19 10:24 ` Claudio Fontana
2021-04-19 10:29 ` Thomas Huth
2021-04-19 10:33 ` Claudio Fontana
2021-04-20 9:34 ` Alex Bennée
2021-04-20 10:53 ` Claudio Fontana
2021-04-16 16:27 ` [RFC v14 53/80] tests: do not run qom-test on all machines for ARM KVM-only Claudio Fontana
2021-04-16 16:27 ` [RFC v14 54/80] Revert "target/arm: Restrict v8M IDAU to TCG" Claudio Fontana
2021-05-05 12:27 ` Philippe Mathieu-Daudé
2021-04-16 16:27 ` [RFC v14 55/80] target/arm: create kvm cpu accel class Claudio Fontana
2021-04-16 16:28 ` [RFC v14 56/80] target/arm: move kvm post init initialization to kvm cpu accel Claudio Fontana
2021-04-16 16:28 ` [RFC v14 57/80] target/arm: add tcg cpu accel class Claudio Fontana
2021-04-16 16:28 ` [RFC v14 58/80] target/arm: move TCG gt timer creation code in tcg/ Claudio Fontana
2021-04-16 16:28 ` [RFC v14 59/80] target/arm: cpu-sve: new module Claudio Fontana
2021-04-16 16:28 ` [RFC v14 60/80] target/arm: cpu-sve: rename functions according to module prefix Claudio Fontana
2021-04-16 16:28 ` [RFC v14 61/80] target/arm: cpu-sve: split TCG and KVM functionality Claudio Fontana
2021-04-16 16:28 ` [RFC v14 62/80] target/arm: cpu-sve: make cpu_sve_finalize_features return bool Claudio Fontana
2021-04-16 16:28 ` [RFC v14 63/80] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 Claudio Fontana
2021-04-16 16:28 ` [RFC v14 64/80] target/arm: restrict rebuild_hflags_a64 to TARGET_AARCH64 Claudio Fontana
2021-04-16 16:28 ` [RFC v14 65/80] target/arm: arch_dump: restrict ELFCLASS64 to AArch64 Claudio Fontana
2021-04-16 16:28 ` [RFC v14 66/80] target/arm: cpu-exceptions, cpu-exceptions-aa64: new modules Claudio Fontana
2021-04-16 16:28 ` [RFC v14 67/80] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64 Claudio Fontana
2021-04-16 16:28 ` [RFC v14 68/80] target/arm: tcg-sve: import narrow_vq and change_el functions Claudio Fontana
2021-04-16 16:28 ` [RFC v14 69/80] target/arm: tcg-sve: rename the " Claudio Fontana
2021-04-16 16:28 ` [RFC v14 70/80] target/arm: move sve_zcr_len_for_el to TARGET_AARCH64-only cpu-sve Claudio Fontana
2021-04-16 16:28 ` [RFC v14 71/80] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el Claudio Fontana
2021-04-16 16:28 ` [RFC v14 72/80] target/arm: cpu-common: wrap a64-only check with is_a64 Claudio Fontana
2021-04-16 16:28 ` [RFC v14 73/80] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication Claudio Fontana
2021-04-16 16:28 ` [RFC v14 74/80] target/arm: cpu-pauth: change arm_cpu_pauth_finalize name and sig Claudio Fontana
2021-04-16 16:28 ` [RFC v14 75/80] target/arm: move arm_cpu_finalize_features into cpu64 Claudio Fontana
2021-04-16 16:28 ` [RFC v14 76/80] target/arm: cpu64: rename arm_cpu_finalize_features Claudio Fontana
2021-04-16 16:28 ` [RFC v14 77/80] target/arm: cpu64: some final cleanup on aarch64_cpu_finalize_features Claudio Fontana
2021-04-16 16:28 ` [RFC v14 78/80] XXX target/arm: experiment refactoring cpu "max" Claudio Fontana
2021-04-16 16:28 ` [RFC v14 79/80] target/arm: tcg: remove superfluous CONFIG_TCG check Claudio Fontana
2021-04-16 16:28 ` [RFC v14 80/80] target/arm: remove v7m stub function for !CONFIG_TCG Claudio Fontana
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